Micron MT66R7072A10AB5ZZW 1 Gbit Phase Change Memory 45 nm BiCMOS PCM Process
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1 Micron MT66R7072A10AB5ZZW 45 nm BiCMOS PCM Process Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:
2 Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PPR JMRK Revision 1.0 Published: April 8, 2013
3 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product 2.2 Package 2.3 U57M Mobile LPDDR2 and IMOLA PCM Dies 2.4 IMOLA PCM Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Transistors and Poly 3.7 Phase Change Memory Layers 3.8 Isolation 3.9 Wells and Substrate 4 PCM Cell Analysis 4.1 Overview 4.2 Plan-View Analysis 4.3 Cross-Sectional Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
4 Overview Overview 1.1 List of Figures 2 Device Overview Smartphone Tilt View Smartphone Front Smartphone Back Smartphone Battery Pack Main Circuit Board Front Main Circuit Board Back Package Top Package Bottom Package X-Ray Top Package X-Ray Side U57M Mobile LPDDR2 Die U57M Mobile LPDDR2 Die Markings IMOLA PCM Die IMOLA PCM Die Markings Annotated Photograph of the IMOLA PCM Die Delayered to Poly IMOLA Die Cross Sections Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Bond Pads PCM Tile Top Metal PCM Tile Poly 3 Process Analysis IMOLA PCM Die General View Die Edge Die Edge Detail Bond Pad Right Bond Pad Edge Passivation Passivation Over Closely Spaced Metal 4 Lines TEM IMD ILD ILD TEM PMD Periphery (Die A) TEM PMD Periphery (Die B) SEM PMD Memory Array to Periphery Transition TEM PMD Memory Array to Periphery Transition TEM PMD PCM Memory Array Minimum Pitch Metal 4 SEM Metal 4 Barrier TEM
5 Overview Minimum Pitch Metal 3 SEM Metal 3 TEM Metal 3 Liner TEM Minimum Pitch Metal 2 in Periphery SEM Metal 2 in Memory Array TEM Minimum Pitch Metal 1 (Die A) in Periphery SEM Minimum Pitch Metal 1 (Die A) in Memory Array SEM Metal 1 (Die A) Detail in Periphery TEM Metal 1 (Die A) Bottom and Liner Detail TEM Metal 1 (Die B) Detail in Logic TEM Minimum Pitch Via 3s Minimum Pitch Via 2 SEM Minimum Pitch Via 1s in Periphery SEM Minimum Pitch Via 1s in Periphery TEM Minimum Pitch Contacts in Periphery TEM Contact in Periphery (Die A) TEM Contact in Periphery Top TEM Contact in Periphery Bottom W Plug Stack (Via 1/Contact 1/Contact 0) in Memory Array TEM W Contact 0 Interface with Substrate Diffusion in Memory Array TEM W Contact 1 Interface with W Contact 0 in Memory Array TEM W Via 1 Interface with W Contact 1 in Memory Array TEM W Via 1 Interface with Metal 1 in Memory Array TEM Minimum Contacted Gate Pitch Minimum Gate Length MOS Transistor TEM Right Edge and Sidewall Spacer Structure of a MOS Transistor TEM Logic Transistor Gate Oxide TEM Peripheral Long Gate Transistor TEM Peripheral Long Gate Sidewall Spacer TEM Peripheral Long Gate Transistor Gate Oxide TEM Minimum Gate Length NMOS Transistors Minimum Gate Length PMOS Transistors PCM Cell Schematic TEM Cross Section of PCM Cell (Length) SEM Cross Section of PCM Cell (Si Stain) Gap Between PCM Cells TEM PCM Top Electrode Contact PCM (Length) GST TEM-EDS PCM TEM (Width) PCM Layers in Detail TEM (Width) PCM Over Nitride Pedestal in Detail (Width) Heater Intersection with GST PCM Layer Heater TEM-EDS Poly Over Isolation
6 Overview STI Wordlines STI Bitlines Wells Periphery to PCM Transition SCM P-Epi and P-Type Substrate SEM (Si Stain) Epi and Substrate SRP Array P-Well SRP SEM N + Base, N - Base, and P + Emitter Si Stain with Etch Conditions of Type A (Perpendicular to PCM Line) SEM N + Base, N - Base, and P + Emitter Si Stain with Etch Conditions of Type B (Perpendicular to PCM Line) P + Emitter and N - Base SEM (Parallel to PCM Line) P + Emitter and N - Base SCM (Parallel to PCM Line) N + Base and N - Base SEM (Parallel to PCM Line) Peripheral N-Well 2 and P-Well SCM Peripheral P-Well and N-Well 2 SRP Peripheral N-Well 1 and N-Well 2 SRP 4 PCM Cell Analysis PCM Schematic Circuit PCM Array Edge at Metal 3 to Metal 2 Transition Metal 2 Wordlines and Bitlines Metal 2 Wordlines Detail Metal 2 Wordlines to Metal 1 Bitlines Transition Metal 1 Bitlines Overview at the Array Edge Metal 1 Bitlines Detail Contacts to the Base (Wordline) and Emitter of BJT Overview Contacts to the Base (Wordline) and Emitter of BJT Detail Memory Array at Interface Between Contact and Diffusion PCM at Diffusion PCM Overview Cross Section (Parallel to Metal 2 Wordline) Active PCM Cells Detailed Cross Section (Parallel to Metal 2 Wordline) Dummy PCM Cells at Memory Array to Periphery Transition (Parallel to Wordline) PCM Overview Cross Section (Parallel to Metal 1 Bitline) PCM Detailed Cross Section (Edge of PCM Line) Dummy PCM Cells at Memory Array to Periphery Transition (Parallel to Bitlines)
7 Overview List of Tables 1 Overview Device Identification Device Summary IMOLA Die Device Summary Process Summary 2 Device Overview Functional Block Sizes Package, Die, and Bond Pad Sizes 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor Horizontal Dimensions Transistor and Polycide Vertical Dimensions PCM Stack Vertical Dimensions PCM Stack Horizontal Dimensions STI Vertical Dimensions STI Horizontal Dimensions Die Thickness, Well Depths, and Doping Concentrations 4 PCM Cell Analysis PCM Cell Dimensions 5 Critical Dimensions Package, Die, and Bond Pad Sizes Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor Horizontal Dimensions PCM Stack Horizontal Dimensions PCM Cell Dimensions STI Horizontal Dimensions Dielectric Thicknesses Metallization Vertical Dimensions Transistor and Polycide Vertical Dimensions PCM Stack Vertical Dimensions STI Vertical Dimensions Die Thickness and Well Depths
8 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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