Samsung S5K3BAFB 2 Megapixel CMOS Image Sensor 0.13 µm Copper CMOS Process Process Review Report
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1 October 13, 2006 Samsung S5K3BAFB 2 Megapixel CMOS Image Sensor 0.13 µm Copper CMOS Process Process Review Report (with Optional TEM Analysis) For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 Process Review Report Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metals 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 Embedded SRAM Analysis 5.1 Cell Schematic 5.2 SRAM Plan-View Analysis 6 Materials Analysis 6.1 TEM-EDS Analysis of the Lenses and Optical Layers 6.2 TEM-EDS Analysis of the Inter-level Dielectrics 6.3 TEM-EDS Analysis of the MIM Capacitor 6.4 Transistors and Contacts
3 Process Review Report 7 ToF-SIMS Analysis of Lenses and Filters 7.1 ToF-SIMS Methodology 7.2 ToF-SIMS Results 8 Critical Dimensions 8.1 Package and Die 8.2 Vertical Dimensions 8.3 Horizontal Dimensions 9 References Report Evaluation
4 Overview Overview 1.1 List of Figures 2 Package and Die MCNEX CIS Assembly Tilt-View MCNEX CIS Assembly Top-View MCNEX CIS Assembly Open-View MCNEX CIS Assembly Bottom-View MCNEX CIS Assembly Top-View Die Photograph Die Markings Annotated Die Photograph Die Corner a Intact Pixel Array Corner Intact Die Corner a Die Corner b Die Corner c Die Corner d Minimum Pitch Bond Pads Single Bond Pad Detail SRAM Block Pixel Array Corner Die Thickness 3 Process Array Edge General Structure Peripheral General Structure Die Edge Cut-Out and Dielectrics Detail Organic Spacer Edge Blue Color Filter Edge Bond Pad Bond Pad Edge Bond Pad Edge Detail Passivation Oxide ILD ILD ILD ILD ILD 1 TEM ILD 1 Detail TEM PMD and STI Metal Minimum Pitch Metal Metal 4 Seal TEM Minimum Pitch Metal 3
5 Overview Minimum Pitch Metal Metal 2 Ta-Based Liner TEM MIM Capacitors on Metal MIM Capacitor Detail TEM Minimum Pitch Metal Metal 1 TEM Metal 1 Ta-Based Liner TEM Minimum Pitch Via 3s Minimum Pitch Via 2s Via 2 TEM Minimum Pitch Via 1s Minimum Pitch Contacts to Polysilicon Contact to Polysilicon TEM Contact to Polycide TEM Minimum Pitch Contacts to Substrate Contact Top TEM Contact Bottom TEM Peripheral Contact TEM Peripheral MOS Transistor (Glass-Etch) Peripheral NMOS (Si-Etch) Peripheral PMOS (Si-Etch) Peripheral Transistor TEM Peripheral Gate Oxide TEM Pixel Array NMOS Transistor (Glass-Etch) Pixel Array NMOS Transistor TEM Pixel Array NMOS Transistor Spacing TEM Pixel Array NMOS Gate Oxide TEM Minimum Width STI STI TEM Poly over STI TEM Peripheral Wells Peripheral Wells SCM SRP Peripheral N-Well SRP Peripheral P-Well Pixel Array P-Well 4 Pixel Array Analysis Pixel Schematic Circuit Pixel Array Corner Optical Pixel Array Lenses Pixel Array Lenses AFM Tilt-View Pixel Array Lenses AFM Cross-Section Pixel Array at Metal Pixel Array at Metal Pixel Array at Metal Pixel Array at Poly
6 Overview Pixel Array at Substrate Pixel Array at Photocathode SCM Pixel at Poly Showing Cross-Sectional Planes Plan-View Pixel Array General Structure (S1) Pixel Array Dielectric Structure (S1) Pixel Array Dielectric Structure TEM (S1) Sealant Layer over ILD 3-1 TEM (S1) Pixel Array Bottom Edge (S1) Pixel Array Top Edge (S1) Pixel Array Bottom Edge Detail (S1) Pixel Read Out Transistors (S1) Lenses and Red Color Filters (S1) Lenses and Green Color Filters (S1) Lenses and Blue Color Filters (S1) Lenses and Color Filters TEM (S1) Pixel and T1 Transfer Transistor (S2) T1 Transfer Transistor Detail (S1) T1 Transfer Transistor Gate Contact (S2) T1 Transfer Transistor Maximum Length (S1) T1 Transfer Transistor Edge TEM (S1) T1 Transfer Transistor Minimum Width (S1) Pixel Through Transfer Transistors and Pixel SCM (S2) Transistors T2, T3 and T4 (Glass-Etch; S1) Transistors T2, T3 and T4 (Si-Etch; S1) T2 Reset Transistors Length TEM (S1) T2 Reset Transistor Width (S2) T3 Source Follower Transistor TEM (S1) T3 Source Follower Transistor Width (S2) T4 Row Select Transistor TEM (S1) T4 Row Select Transistor Width (S2) T2, T3 and T4 Gate Contacts (S1) Column Out Contact (S2) MIM Cap (S1) MIM Cap (S2) 5 Embedded SRAM Analysis T-SRAM Cell SRAM at Metal SRAM at Metal SRAM at Poly SRAM at Diffusion
7 Overview Materials Analysis Lens Assembly TEM TEM-EDS Passivation and Lenses TEM-EDS Organic Spacer Layers TEM-EDS Filter A and B TEM-EDS Pixel Mesa Filler TEM-EDS ILD 4-2 and ILD 4-1 Dielectrics TEM-EDS ILD 3-3 and ILD 3-2 Line Dielectrics TEM-EDS ILD 3-2 and 3-1 Via Dielectrics TEM-EDS ILD 2-2 and ILD 2-1 Via Dielectrics TEM-EDS ILD 1-4 and ILD 1-3 Line Dielectrics TEM-EDS ILD 1-2 and ILD 1-1 Via Dielectrics TEM-EDS PMD 5 and PMD 4 Dielectrics TEM-EDS PMD 3, PMD 2 and PMD 1 Dielectrics TEM-EDS Capacitor Dielectric and Hard Mask TEM-EDS Capacitor Plates Transistor EDS Analyses Areas TEM-EDS Top of Buffer Oxide TEM-EDS Contact Liner TEM-EDS Contact Bottom SEM-EDS Peripheral Transistors 7 ToF-SIMS Analysis of Lenses and Filters Negative Ion ToF-SIMS Depth Profile Negative Ion ToF-SIMS Image of Color Filters
8 Overview List of Tables 1 Overview Device Summary Summary of Major Findings 2 Package and Die Package and Die Dimensions 3 Process Dielectric Composition and Thicknesses Metallization Composition and Thicknesses Minimum Metal Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor and Polysilicon Horizontal Dimensions Transistor and Polysilicon Vertical Dimensions Isolation Horizontal Dimension Wells and Epi Vertical Dimensions 4 Pixel Array Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Transistor Dimensions in Pixel Array 5 Embedded SRAM Analysis SRAM Transistor Sizes 6 Materials Analysis Summary of TEM-EDS Analysis Results for Dielectrics and Organic Layers 7 ToF-SIMS Analysis of Lenses and Filters Summary of Color Filter Composition 8 Critical Dimensions Package and Die Dimensions Dielectric Composition and Thicknesses Metallization Composition and Thicknesses Transistor and Polysilicon Vertical Dimensions Wells and Epi Vertical Dimensions Minimum Metal Horizontal Dimensions Via and Contact Horizontal Dimensions Transistor and Polysilicon Horizontal Dimensions Isolation Horizontal Dimension Pixel Horizontal Dimensions
9 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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