Chapter 15 Summary and Future Trends

Size: px
Start display at page:

Download "Chapter 15 Summary and Future Trends"

Transcription

1 Chapter 15 Summary and Future Trends Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1

2 The 1960s First IC product Bipolar dominant PMOS Diffusion for doping Metal gate Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 2

3 PMOS in the 1960s Gate Oxide CVD Cap Oxide p + N-Silicon p + Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 3

4 The 1970s Bipolar dominant NMOS Ion implantation for doping after mid-1970s Self-aligned source/drain Polysilicon gate Main driving force: electronic watches and calculators Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 4

5 NMOS in the 1970s Al Si SiN PSG Poly n + p-si n + Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 5

6 The 1980s MOSFET surpassed bipolar CMOS Multi-level interconnections Main driving force: personal computer Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 6

7 CMOS in the 1980s PD2 Nitride PD1 Oxide Metal 2, Al Cu Si p + n + IMD PMD Poly Si Gate n + Al Cu Si BPSG LOCOS SiO 2 p + P-type substrate USG dep/etch/dep p + p + N-well Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 7

8 The 1990s MOSFET dominant CMOS Multi-level interconnections Tungsten Silicide CMP Main driving force: PC, network, internet Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 8

9 CMOS Passivation 2 Silicon Nitride in the Al Cu Alloy Al Cu Passivation 1 USG 1990s Ti/TiN IMD 3 USG Metal 4 TiN ARC Metal 3 Al Cu Alloy Ti Ti/TiN IMD 2 USG W M2 Al Cu IMD 1 USG W TiSi 2 M1 Al Cu Alloy Sidewall Spacer, USG PMD W BPSG Poly-Si STI n + n + USG p + p + P-Well N-Well Hong Xiao, Ph. D. P-Epi www2.austin.cc.tx.us/hongxiao/book.htm P-Wafer 9 PMD Barrier Nitride

10 The 2000s MOSFET dominant CMOS SOI substrate Copper and low-κ interconnection Main driving force: telecommunication, network, internet, PC Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 10

11 CMOS Cr, Cu, and Au liners Copper 5 Lead-tin alloy SOD Nitride PSG SiN seal layer in the SOD SOD Copper s SiC etch stop layers SOD Ta/TaN barrier layer Cu 3 SOD Cu 3 CoSi 2 Copper 2 Cu 1 Cu 1 SOD Cu 1 Cu 1 W Tungsten PSG n + P-well n + p + N-well p + Buried SiO 2 P-wafer Poly Si gate SiN barrier Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm STI USG USG layer 11 SOD SOD SOD SOD SiC seal layer PE-TEOS cap SiC seal layer

12 New Materials: Copper Metal interconnection: Cu replace Al and W Lower resistivity Improve device speed Higher electromigration resistance Higher current Reduce metal layers that reduce processing steps Lower the production cost Improves overall yield Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 12

13 New Materials: Low-κ Low-κ dielectrics replace silicate glass for the interconnection applications CVD: CSG and α-fc SOD: HSQ and porous silica. Combination of copper and low-κ to improves IC chip speed Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 13

14 New Materials: High-κ Capacitance of MOS gate capacitor has to be large enough to hold enough charges Feature size reducing, gate capacitance reduces High-κ, thicker gate dielectric to prevent the leakage and breakdown Candidates: TiO 2 (κ ~ 60), Ta 2 O 5 (κ ~ 25), and possibly HfO 2 Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 14

15 New Materials: High-κ BST (Ba ½ Sr ½ TiO 3, κ up to 600 DRAM capacitor dielectric Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 15

16 Next Generation Lithography Photolithography limit: ~ nm, after 2010 Next generation lithography (NGL) technology EUV lithography Projection electron beam lithography Still in R&D Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 16

17 Developing Industry After more than 50 years, semiconductor industry is still a developing industry, not a matured industry as automobile industry New technology is introduced almost daily Technology less than ten years could become obsolete Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 17

18 300 mm and Beyond Larger wafer size, more chip can be made Currently 300 mm (12 inch) transition Will become mainstream Cost more than 2 billion dollar to build 400 mm wafer fabs may start by 2010 Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 18

19 World Chip Demands Lower chip price, cheaper consumer electronics TVs, VCRs, telephones, and PCs. Steady economy development of developing country, especially China and India Dramatically increase the demands Need more chips! Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 19

20 Auto-chip Global location system and voice activated internet access may become standard feature in the future automobiles In the near future, General Motors (GM) will consume more IC chips than International Business Machines (better known as IBM) every year Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 20

21 Bio-chip Miniaturize test probes and analysis circuits Medical IC chips for DNA test Fast, accurate diagnosis of DNA related diseases. Lab-on-chip Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 21

22 Telecommunication, Internet The worldwide development of the telecommunication and internet will still be the main driving force of the continuing rapid development of the IC industry in the near future Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 22

23 Future is Bright Boom-bust cycle of the IC industry Demands for IC chips will steadily grow So will the demands for skillful and knowledgeable workers Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 23

24 Life After the Final Limit Physical limit may be reached by ~2030 Feature size 10 to 5 nm IC feature size can no longer shrink IC industry will finally become matured Less frequent technology change Still need large number of workers, just like auto industry Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 24

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and

More information

2.8 - CMOS TECHNOLOGY

2.8 - CMOS TECHNOLOGY CMOS Technology (6/7/00) Page 1 2.8 - CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical

More information

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught

More information

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1

Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught

More information

EE 410: Integrated Circuit Fabrication Laboratory

EE 410: Integrated Circuit Fabrication Laboratory EE 410: Integrated Circuit Fabrication Laboratory 1 EE 410: Integrated Circuit Fabrication Laboratory Web Site: Instructor: http://www.stanford.edu/class/ee410 https://ccnet.stanford.edu/ee410/ (on CCNET)

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

nvidia GeForce FX 5700 Ultra (NV36) Graphics Processor Structural Analysis

nvidia GeForce FX 5700 Ultra (NV36) Graphics Processor Structural Analysis nvidia GeForce FX 5700 Ultra (NV36) Graphics Processor Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information

Samsung K4H510838C-UCCC 512Mbit DDR SDRAM Structural Analysis

Samsung K4H510838C-UCCC 512Mbit DDR SDRAM Structural Analysis July 26, 2005 Samsung K4H510838C-UCCC 512Mbit DDR SDRAM Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor

More information

Peregrine Semiconductor PE4268 SP6T RF UltraCMOS TM Switch Structural Analysis

Peregrine Semiconductor PE4268 SP6T RF UltraCMOS TM Switch Structural Analysis September 21, 2005 Peregrine Semiconductor PE4268 Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology,

More information

Matrix Semiconductor One Time Programmable Memory

Matrix Semiconductor One Time Programmable Memory December 22, 2004 Matrix Semiconductor 11247-01-99 One Time Programmable Memory Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

Spansion S29GL512N11TAI Mbit MirrorBit TM Flash Memory Structural Analysis

Spansion S29GL512N11TAI Mbit MirrorBit TM Flash Memory Structural Analysis March 5, 2007 Spansion S29GL512N11TAI02 512 Mbit MirrorBit TM Flash Memory Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning

More information

(a) (d) (e) (b) (c) (f) 3D-NAND Flash and Its Manufacturing Process

(a) (d) (e) (b) (c) (f) 3D-NAND Flash and Its Manufacturing Process 3D-NAND Flash and Its Manufacturing Process 79 (d) Si Si (b) (c) (e) Si (f) +1-2 (g) (h) Figure 2.33 Top-down view in cap oxide and (b) in nitride_n-2; (c) cross-section near the top of the channel; top-down

More information

Samsung K4B1G0846F-HCF8 1 Gbit DDR3 SDRAM 48 nm CMOS DRAM Process

Samsung K4B1G0846F-HCF8 1 Gbit DDR3 SDRAM 48 nm CMOS DRAM Process Samsung K4B1G0846F-HCF8 48 nm CMOS DRAM Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics

More information

Samsung S5K3BAFB 2 Megapixel CMOS Image Sensor 0.13 µm Copper CMOS Process Process Review Report

Samsung S5K3BAFB 2 Megapixel CMOS Image Sensor 0.13 µm Copper CMOS Process Process Review Report October 13, 2006 Samsung S5K3BAFB 2 Megapixel CMOS Image Sensor 0.13 µm Copper CMOS Process Process Review Report (with Optional TEM Analysis) For comments, questions, or more information about this report,

More information

Toshiba TH58NVG2S3BTG00 4 Gbit NAND Flash Structural Analysis

Toshiba TH58NVG2S3BTG00 4 Gbit NAND Flash Structural Analysis July 5, 2005 Toshiba TH58NVG2S3BTG00 4 Gbit NAND Flash Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor

More information

Silicon Storage Technology SST39VF800A 8 Mbit Multi-Purpose Flash Memory Structural Analysis

Silicon Storage Technology SST39VF800A 8 Mbit Multi-Purpose Flash Memory Structural Analysis February 23, 2005 Silicon Storage Technology SST39VF800A 8 Mbit Multi-Purpose Flash Memory Structural Analysis For questions, comments, or more information about this report, or for any additional technical

More information

Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7

Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7 Color Plates SIMULATION OF SEMICONDUCTOR LITHOGRAPHY AND TOPOGRAPHY - ARN 7 FIGURE CP.1 Layout and cross section of an N-Well CMOS process using 2D models in SIMPL-2 [rzz.lee.phd]. FIGURE CP.2 Magnified

More information

Maxim MAX3940E Electro-Absorption Modulator Structural Analysis

Maxim MAX3940E Electro-Absorption Modulator Structural Analysis May 23, 2006 Maxim MAX3940E Electro-Absorption Modulator Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor

More information

Innovation to Advance Moore s Law Requires Core Technology Revolution

Innovation to Advance Moore s Law Requires Core Technology Revolution Innovation to Advance Moore s Law Requires Core Technology Revolution Klaus Schuegraf, Ph.D. Chief Technology Officer Silicon Systems Group Applied Materials UC Berkeley Seminar March 9 th, 2012 Innovation

More information

LSI ON GLASS SUBSTRATES

LSI ON GLASS SUBSTRATES LSI ON GLASS SUBSTRATES OUTLINE Introduction: Why System on Glass? MOSFET Technology Low-Temperature Poly-Si TFT Technology System-on-Glass Technology Issues Conclusion System on Glass CPU SRAM DRAM EEPROM

More information

Xilinx XC5VLX50 FPGA UMC 65 nm Process

Xilinx XC5VLX50 FPGA UMC 65 nm Process Xilinx XC5VLX50 FPGA UMC 65 nm Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor and electronics

More information

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI

Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives

More information

FUTURE PROSPECTS FOR CMOS ACTIVE PIXEL SENSORS

FUTURE PROSPECTS FOR CMOS ACTIVE PIXEL SENSORS FUTURE PROSPECTS FOR CMOS ACTIVE PIXEL SENSORS Dr. Eric R. Fossum Jet Propulsion Laboratory Dr. Philip H-S. Wong IBM Research 1995 IEEE Workshop on CCDs and Advanced Image Sensors April 21, 1995 CMOS APS

More information

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 40 BICMOS technology So, today we are going to have the last class on this VLSI

More information

Chapter 1, Introduction

Chapter 1, Introduction Introduction to Semiconductor Manufacturing Technology Chapter 1, Introduction hxiao89@hotmail.com 1 Objective After taking this course, you will able to Use common semiconductor terminology Describe a

More information

Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy

Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy Process Control Limits in a CMOS ASIC Fabrication Process K. Jayavel, K.S.R.C.Murthy Society for Integrated circuit Technology and Applied Research Centre (SITAR), 1640, Doorvaninagar, Bangalore, Karnataka,

More information

IWORID J. Schmitz page 1. Wafer-level CMOS post-processing Jurriaan Schmitz

IWORID J. Schmitz page 1. Wafer-level CMOS post-processing Jurriaan Schmitz IWORID J. Schmitz page 1 Wafer-level CMOS post-processing Jurriaan Schmitz IWORID J. Schmitz page 2 Outline Introduction on wafer-level post-proc. CMOS: a smart, but fragile substrate Post-processing steps

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm

Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline

More information

Newer process technology (since 1999) includes :

Newer process technology (since 1999) includes : Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks

More information

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978)

IC Knowledge LLC, PO Box 20, Georgetown, MA Ph: (978) , Fx: (978) IC Knowledge LLC, PO Box 20, Georgetown, MA 01833 www.icknowledge.com Ph: (978) 352 7610, Fx: (978) 352 3870 Linx Consulting, PO Box 384, Mendon, MA 01756 0384 www.linxconsulting.com Ph: (617) 273 8837

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

EE C245 ME C218 Introduction to MEMS Design

EE C245 ME C218 Introduction to MEMS Design EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 7: Noise &

More information

Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M 512 Megabit DDR2 SDRAM Structural Analysis

Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M 512 Megabit DDR2 SDRAM Structural Analysis February 23, 2007 Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning

More information

Analog Devices AD7658 Analog to Digital Converter icmos Process Technology Process Review

Analog Devices AD7658 Analog to Digital Converter icmos Process Technology Process Review November 1, 2005 Analog Devices AD7658 Analog to Digital Converter icmos Process Technology Process Review For comments, questions, or more information about this report, or for any additional technical

More information

Samsung K9F2G08U0M-YCB0 2Gbit NAND Flash Device Structural Analysis

Samsung K9F2G08U0M-YCB0 2Gbit NAND Flash Device Structural Analysis April 4, 2006 Samsung K9F2G08U0M-YCB0 2Gbit NAND Flash Device Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor

More information

PowerDsine/Freescale

PowerDsine/Freescale April 25, 2005 PowerDsine/Freescale PD64004 4 Channel Power-Over-Ethernet (POE) Manager Process Review For questions, comments, or more information about this report, or for any additional technical needs

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

INF4420 Layout and CMOS processing technology

INF4420 Layout and CMOS processing technology INF4420 Layout and CMOS processing technology Spring 2012 Jørgen Andreas Michaelsen (jorgenam@ifi.uio.no) Outline CMOS Fabrication overview Design rules Layout of passive and active componets Packaging

More information

LSI Logic LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Controller 0.18 µm CMOS Process

LSI Logic LSI53C1030 PCI-X to Dual Channel Ultra320 SCSI Controller 0.18 µm CMOS Process LSI Logic LSI53C13 PCI-X to Dual Channel Ultra32 SCSI Controller.18 µm CMOS Process Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs

More information

Olympus EVOLT E-410/Matsushita LiveMOS Image Sensor

Olympus EVOLT E-410/Matsushita LiveMOS Image Sensor Olympus EVOLT E-410/Matsushita Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

Nanya elixir N2TU51280AF-37B 512 Mbit DDR2 SDRAM Structural Analysis

Nanya elixir N2TU51280AF-37B 512 Mbit DDR2 SDRAM Structural Analysis September 20, 2005 Nanya elixir N2TU51280AF-37B 512 Mbit DDR2 SDRAM Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning

More information

Sony IMX Megapixel, 1.4 µm Pixel 1/3.2 Optical Format CMOS Image Sensor

Sony IMX Megapixel, 1.4 µm Pixel 1/3.2 Optical Format CMOS Image Sensor Sony IMX046 8.11 Megapixel, 1.4 µm Pixel 1/3.2 Optical Format CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs

More information

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 PROBLEM SET #2. Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory.

EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 PROBLEM SET #2. Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory. Issued: Tuesday, Sept. 13, 2011 PROBLEM SET #2 Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory. 1. Below in Figure 1.1 is a description of a DRIE silicon etch using the Marvell

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor

Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

Layout and technology

Layout and technology INF4420 Layout and technology Dag T. Wisland Spring 2015 Outline CMOS technology Design rules Analog layout Mismatch Spring 2015 Layout and technology 2 Introduction As circuit designers we must carefully

More information

Device Technologies. Yau - 1

Device Technologies. Yau - 1 Device Technologies Yau - 1 Objectives After studying the material in this chapter, you will be able to: 1. Identify differences between analog and digital devices and passive and active components. Explain

More information

MagnaChip MC511DB 1.3 Megapixel CMOS Image Sensor 0.18 µm Process

MagnaChip MC511DB 1.3 Megapixel CMOS Image Sensor 0.18 µm Process MagnaChip MC511DB 1.3 Megapixel CMOS Image Sensor 0.18 µm Process Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning

More information

Microsoft X02046 IBM PowerPC Processor from the XBOX 360 Structural Analysis

Microsoft X02046 IBM PowerPC Processor from the XBOX 360 Structural Analysis February 7, 2006 Microsoft X02046 IBM PowerPC Processor from the XBOX 360 Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning

More information

Intel s High-k/Metal Gate Announcement. November 4th, 2003

Intel s High-k/Metal Gate Announcement. November 4th, 2003 Intel s High-k/Metal Gate Announcement November 4th, 2003 1 What are we announcing? Intel has made significant progress in future transistor materials Two key parts of this new transistor are: The gate

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Panasonic DMC-GH Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera

Panasonic DMC-GH Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera Panasonic DMC-GH1 12.1 Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera Imager Process Review For comments, questions, or more

More information

Panasonic DMC-GH Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera

Panasonic DMC-GH Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera Panasonic DMC-GH1 12.1 Mp, 4.4 µm Pixel Size LiveMOS Image Sensor from Panasonic LUMIX DMC-GH1 Micro Four Thirds Digital Interchangeable Lens Camera Imager Process Review For comments, questions, or more

More information

Samsung K9HAG08U1M-PCB0 16 Gbit MLC NAND Flash Structural Analysis Report

Samsung K9HAG08U1M-PCB0 16 Gbit MLC NAND Flash Structural Analysis Report March 6, 2006 Samsung K9HAG08U1M-PCB0 16 Gbit MLC NAND Flash Structural Analysis Report For comments, questions, or more information about this report, or for any additional technical needs concerning

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

Module 2: CMOS FEOL Analysis

Module 2: CMOS FEOL Analysis Module 2: CMOS FEOL Analysis Manufacturer Device # 2 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems.

More information

Photolithography I ( Part 1 )

Photolithography I ( Part 1 ) 1 Photolithography I ( Part 1 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science

More information

Digital Integrated Circuit Design I ECE 425/525 Chapter 3

Digital Integrated Circuit Design I ECE 425/525 Chapter 3 Digital Integrated Circuit Design I ECE 425/525 Chapter 3 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25

More information

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations

ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Workshop on Frontiers of Extreme Computing Santa Cruz, CA October 24, 2005 ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Peter M. Zeitzoff Outline Introduction MOSFET scaling and

More information

Micron MT66R7072A10AB5ZZW 1 Gbit Phase Change Memory 45 nm BiCMOS PCM Process

Micron MT66R7072A10AB5ZZW 1 Gbit Phase Change Memory 45 nm BiCMOS PCM Process Micron MT66R7072A10AB5ZZW 45 nm BiCMOS PCM Process Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com Process Review Some of the information in

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,

More information

Chapter 3. Digital Integrated Circuit Design I. ECE 425/525 Chapter 3. Substrates in MOS doped n or p type Silicon (Chemical.

Chapter 3. Digital Integrated Circuit Design I. ECE 425/525 Chapter 3. Substrates in MOS doped n or p type Silicon (Chemical. Digital Integrated Circuit Design I ECE 425/525 Professor R. Daasch Depar tment of Electrical and Computer Engineering Portland State University Portland, OR 97207-0751 (daasch@ece.pdx.edu) http://ece.pdx.edu/~ecex25

More information

Sony IMX018 CMOS Image Sensor Imager Process Review

Sony IMX018 CMOS Image Sensor Imager Process Review September 6, 2006 Sony IMX018 CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology,

More information

Fault Diagnosis Algorithms Part 2

Fault Diagnosis Algorithms Part 2 Fault Diagnosis Algorithms Part 2 By Christopher Henderson Page 1 Fault Diagnosis Algorithms Part 2 Page 5 Technical Tidbit Page 8 Ask the Experts Figure 4. Circuit schematic. This is an example of a circuit

More information

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore

Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic

More information

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 81 Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness Alpana

More information

New Process Technologies Will silicon CMOS carry us to the end of the Roadmap?

New Process Technologies Will silicon CMOS carry us to the end of the Roadmap? HPEC Workshop 2006 New Process Technologies Will silicon CMOS carry us to the end of the Roadmap? Craig L. Keast, Chenson Chen, Mike Fritze, Jakub Kedzierski, Dave Shaver HPEC 2006-1 Outline A brief history

More information

Samsung K9G8G08U0M-PCB0 8 Gbit MLC NAND Flash Structural Analysis

Samsung K9G8G08U0M-PCB0 8 Gbit MLC NAND Flash Structural Analysis November 6, 2006 Samsung K9G8G08U0M-PCB0 Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please

More information

Texas Instruments BQ29330 Battery Protection AFE from BQ20Z95DBT

Texas Instruments BQ29330 Battery Protection AFE from BQ20Z95DBT Texas Instruments BQ29330 Battery Protection AFE from BQ20Z95DBT Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor

More information

Cypress CY7C PVC USB 2.0 Integrated Microcontroller Process Analysis

Cypress CY7C PVC USB 2.0 Integrated Microcontroller Process Analysis March 12, 2004 Cypress CY7C68013-56PVC USB 2.0 Integrated Microcontroller Process Analysis Introduction... Page 1 List of Figures... Page 2 Device Summary... Page 6 Device Identification Package and Assembly

More information

Lecture Notes 5 CMOS Image Sensor Device and Fabrication

Lecture Notes 5 CMOS Image Sensor Device and Fabrication Lecture Notes 5 CMOS Image Sensor Device and Fabrication CMOS image sensor fabrication technologies Pixel design and layout Imaging performance enhancement techniques Technology scaling, industry trends

More information

VLSI: An Introduction

VLSI: An Introduction Chapter 1 UEEA2223/UEEG4223 Integrated Circuit Design VLSI: An Introduction Prepared by Dr. Lim Soo King 02 Jan 2011. Chapter 1 VLSI Design: An Introduction... 1 1.0 Introduction... 1 1.0.1 Early Computing

More information

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already

EE241 - Spring 2013 Advanced Digital Integrated Circuits. Announcements. Sign up for Piazza if you haven t already EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements Sign up for Piazza if you haven t already 2 1 Assigned Reading R.H.

More information

SPECIAL REPORT SOI Wafer Technology for CMOS ICs

SPECIAL REPORT SOI Wafer Technology for CMOS ICs SPECIAL REPORT SOI Wafer Technology for CMOS ICs Robert Simonton President, Simonton Associates Introduction: SOI (Silicon On Insulator) wafers have been used commercially as starting substrates for several

More information

Session 3: Solid State Devices. Silicon on Insulator

Session 3: Solid State Devices. Silicon on Insulator Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted

More information

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004

A Perspective on Semiconductor Equipment. R. B. Herring March 4, 2004 A Perspective on Semiconductor Equipment R. B. Herring March 4, 2004 Outline Semiconductor Industry Overview of circuit fabrication Semiconductor Equipment Industry Some equipment business strategies Product

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

FinFET vs. FD-SOI Key Advantages & Disadvantages

FinFET vs. FD-SOI Key Advantages & Disadvantages FinFET vs. FD-SOI Key Advantages & Disadvantages Amiad Conley Technical Marketing Manager Process Diagnostics & Control, Applied Materials ChipEx-2014, Apr 2014 1 Moore s Law The number of transistors

More information

Lecture 27 ANNOUNCEMENTS. Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website

Lecture 27 ANNOUNCEMENTS. Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website Lecture 27 ANNOUNCEMENTS Regular office hours will end on Monday 12/10 Special office hours will be posted on the EE105 website Final Exam Review Session: Friday 12/14, 3PM, HP Auditorium Video will be

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 11/01/2007 MOSFETs Lecture 5 Announcements HW7 set is due now HW8 is assigned, but will not be collected/graded. MOSFET Technology Scaling Technology

More information

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141 EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructors: Wawrzynek Lecture 8 EE141 From the Bottom Up IC processing CMOS Circuits (next lecture) EE141 2 Overview of Physical Implementations

More information

Sony IMX118CQT 18.5 Mp, 1.25 µm Pixel Pitch Back Illuminated CIS from the Sony DSC-WX100 Camera

Sony IMX118CQT 18.5 Mp, 1.25 µm Pixel Pitch Back Illuminated CIS from the Sony DSC-WX100 Camera 18.5 Mp, 1.25 µm Pixel Pitch Back Illuminated CIS from the Sony DSC-WX100 Camera Imager Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com Imager

More information

PROCESS INTEGRATION ISSUES OF LOW-PERMITTIVITY DIELECTRICS WITH COPPER FOR HIGH-PERFORMANCE INTERCONNECTS

PROCESS INTEGRATION ISSUES OF LOW-PERMITTIVITY DIELECTRICS WITH COPPER FOR HIGH-PERFORMANCE INTERCONNECTS PROCESS INTEGRATION ISSUES OF LOW-PERMITTIVITY DIELECTRICS WITH COPPER FOR HIGH-PERFORMANCE INTERCONNECTS A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE

More information

Chapter 2 : Semiconductor Materials & Devices (II) Feb

Chapter 2 : Semiconductor Materials & Devices (II) Feb Chapter 2 : Semiconductor Materials & Devices (II) 1 Reference 1. SemiconductorManufacturing Technology: Michael Quirk and Julian Serda (2001) 3. Microelectronic Circuits (5/e): Sedra & Smith (2004) 4.

More information

The Art of ANALOG LAYOUT Second Edition

The Art of ANALOG LAYOUT Second Edition The Art of ANALOG LAYOUT Second Edition Alan Hastings 3 EARSON Pearson Education International Contents Preface to the Second Edition xvii Preface to the First Edition xix Acknowledgments xxi 1 Device

More information

Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures

Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Improving CMOS Speed and Switching Energy with Vacuum-Gap Structures Chenming Hu and Je Min Park Univ. of California, Berkeley -1- Outline Introduction Background and Motivation MOSFETs with Vacuum-Spacer

More information

IBM POWER7 Server 46J6702 IBM 45 nm Dual Stress Liner SOI CMOS Process with edram

IBM POWER7 Server 46J6702 IBM 45 nm Dual Stress Liner SOI CMOS Process with edram IBM POWER7 Server 46J6702 IBM 45 nm Dual Stress Liner SOI CMOS Process with edram Front End Process Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613-829-0414 www.chipworks.com

More information

W ith development risk fully borne by the equipment industry and a two-year delay in the main

W ith development risk fully borne by the equipment industry and a two-year delay in the main Page 1 of 5 Economic Challenges and Opportunities in the 300 mm Transition Iddo Hadar, Jaim Nulman, Kunio Achiwa, and Oded Turbahn, Applied Materials Inc. -- 10/1/1998 Semiconductor International W ith

More information

Outline. Layout and technology. CMOS technology Design rules Analog layout Mismatch INF4420. Jørgen Andreas Michaelsen Spring / 80 2 / 80

Outline. Layout and technology. CMOS technology Design rules Analog layout Mismatch INF4420. Jørgen Andreas Michaelsen Spring / 80 2 / 80 INF4420 Layout and technology Jørgen Andreas Michaelsen Spring 2013 1 / 80 Outline CMOS technology Design rules Analog layout Mismatch Spring 2013 Layout and technology 2 2 / 80 Introduction As circuit

More information