Photolithography I ( Part 1 )

Transcription

1 1 Photolithography I ( Part 1 ) Chapter 13 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Bjørn-Ove Fimland, Department of Electronics and Telecommunication, Norwegian University of Science and Technology ( NTNU )

2 2 Wafer Fabrication Process Flow Wafer fabrication (front-end) Wafer start Thin Films Polish Unpatterned wafer Completed wafer Diffusion Photo Etch Test/Sort Implant Used with permission from Advanced Micro Devices Figure 13.1 Quirk & Serda

3 3 Nanofabrication Steps

4 4 Nanofabrication Steps ( Continue )

5 5 Nanofabrication Steps ( Continue )

6 6 Nanofabrication Steps ( Continue )

7 7 Wafer Fabrication Process Flow Wafer fabrication (front-end) Wafer start Thin Films Polish Unpatterned wafer Completed wafer Diffusion Photo Etch Test/Sort Implant Used with permission from Advanced Micro Devices Figure 13.1 Quirk & Serda

8 8 CMOS Manufacturing Steps 8 LI metal n Via 11 M-4 M-3 9 Passivation layer ILD-6 M-2 M-1 Poly gate 3 LI oxide p + p + STI n + n n-well 10 5 ILD-5 ILD-4 ILD-3 ILD-2 ILD-1 1 p - Epitaxial layer 6 p-well Twin-well Implants Bonding pad metal p + 2. Shallow Trench Isolation 3. Gate Structure 4. Lightly Doped Drain Implants 5. Sidewall Spacer 6. Source/Drain Implants 7. Contact Formation 8. Local Interconnect 9. Interlayer Dielectric to Via First Metal Layer 11. Second ILD to Via Second Metal Layer to Via Metal-3 to Pad Etch 14. Parametric Testing p + Silicon substrate

9 9 Ten steps of Photolithography UV Light HMDS Resist Mask λ λ 1-3) Vapor prime 4) Spin coat 5) Soft bake 6) Alignment and Exposure 7) Post-exposure bake (PEB) 8) Develop 9) Hard bake 10) Develop inspect

10 10 Different Alignments

11 11 Lens Capturing Diffracted Light Quartz UV Mask Chrome Diffraction patterns Lens Figure Quirk and Serda

12 12 Edge Diffraction and Surface Reflectivity on Proximity Aligner UV exposure light Mask UV Mask Diffracted and reflected light Resist Substrate Gap Substrate Diffraction of light on edges results in reflections from underside of mask causing undesirable resist exposure. Figure Quirk and Serda

13 13 Different Alignments

14 14 Stepper Exposure Field UV light Reticle field size 20 mm 15mm, 4 die per field 5:1 reduction lens Serpentine stepping pattern Image exposure on wafer 1/5 of reticle field 4 mm 3 mm, 4 die per exposure Wafer Figure Quirk and Serda

15 15 Photomask and Reticle for Microlithography 1:1 Mask 4:1 Reticle Photograph provided courtesy of Advanced Micro Devices Photo 13.1 Quirk and Serda

16 16 Ten steps of Photolithography UV Light HMDS Resist Mask λ λ 1-3) Vapor prime 4) Spin coat 5) Soft bake 6) Alignment and Exposure 7) Post-exposure bake (PEB) 8) Develop 9) Hard bake 10) Develop inspect

17 17 Three Dimensional Pattern in Photoresist Linewidth Space Photoresist Thickness Substrate Figure 13.2 Quirk and Serda

18 18 Parameters Critical Dimension (CD): Most critical length in a semiconductor device (determines the size of the device, like gate length) Often defined by photolithography If CD can be reduced, more die can be placed on a wafer more cost-efficient Resolution (R): Ability to differentiate between two closely spaced features on the wafer. Smallest feature size possible is critical dimension

19 19 CMOS Manufacturing Steps 8 LI metal n Via 11 M-4 M-3 9 Passivation layer ILD-6 M-2 M-1 Poly gate 3 LI oxide p + p + STI n + n n-well 10 5 ILD-5 ILD-4 ILD-3 ILD-2 ILD-1 1 p - Epitaxial layer 6 p-well Twin-well Implants Bonding pad metal p + 2. Shallow Trench Isolation 3. Gate Structure 4. Lightly Doped Drain Implants 5. Sidewall Spacer 6. Source/Drain Implants 7. Contact Formation 8. Local Interconnect 9. Interlayer Dielectric to Via First Metal Layer 11. Second ILD to Via Second Metal Layer to Via Metal-3 to Pad Etch 14. Parametric Testing p + Silicon substrate

20 20 Component technology nodes (Generations) 130 nm (2001) (Year): Products available in market. Domos earlier. 90 nm (2004) 65 nm (2006) 45 nm (2008) 32 nm (2010) - Intel Core i3 and Core i5 processors 22 nm (2012) - Intel Core i7 (and new Core i5) processors (3D Tri-Gate trans.) 14 nm (2014) - Intel Core M processors (3D Tri-Gate transistors) 10 nm (2016?) 7 nm (2018?) 5 nm (2020?) End of Moore s law??

21 21 Ten steps of Photolithography UV Light HMDS Resist Mask λ λ 1-3) Vapor prime 4) Spin coat 5) Soft bake 6) Alignment and Exposure 7) Post-exposure bake (PEB) 8) Develop 9) Hard bake 10) Develop inspect

22 22 Section of the Electromagnetic Spectrum Visible Gamma rays X-rays UV Infrared Microwaves Radio waves f (Hz) (m) λ λ (nm) VUV DUV DUV i h g Common UV wavelengths used in optical lithography. Figure 13.3 Quirk and Serda

23 23 Important Wavelengths for Photolithography Exposure UV Wavelength (nm) Wavelength Name UV Emission Source 436 g-line Mercury arc lamp 405 h-line Mercury arc lamp 365 i-line Mercury arc lamp 248 Deep UV (DUV) Mercury arc lamp or Krypton Fluoride (KrF) excimer laser 193 Deep UV (DUV) Argon Fluoride (ArF) excimer laser 157 Vacuum UV (VUV) Fluorine (F 2 ) excimer laser Table 13.1 Quirk and Serda

24 24 Photolithography Concepts Patterning Process Photo-mask Reticle Critical Dimension Generations Light Spectrum Resolution Overlay Accuracy Process Latitude

25 25 Negative Lithography Chrome island on glass mask Shadow on photoresist Ultraviolet light Exposed area of photoresist Areas exposed to light become crosslinked and resist the developer chemical. Island Photoresist Window Photoresist Oxide Silicon substrate Oxide Silicon substrate Resulting pattern after the resist is developed. Figure 13.5 Quirk and Serda

26 26 Positive Lithography Ultraviolet light Chrome island on glass mask Shadow on photoresist Areas exposed to light are dissolved. Island Window Exposed area of photoresist photoresist Photoresist Photoresist photoresist Oxide oxide Silicon silicon substrate Oxide oxide Silicon silicon substrate Resulting pattern after the resist is developed. Figure 13.6 Quirk and Serda

27 27 Relationship between Mask and Resist Desired photoresist structure to be printed on wafer Island of photoresist Substrate Chrome Window Quartz Island Mask pattern required when using negative photoresist (opposite of intended structure) Mask pattern required when using positive photoresist (same as intended structure) Figure 13.7 Quirk and Serda

28 28 Clear Field and Dark Field Masks Clear Field Mask Dark Field Mask Simulation of metal interconnect lines (positive resist lithography) Simulation of contact holes (positive resist lithography) Figure 13.8 Quirk and Serda

29 29 Negative versus Positive Resist Negative Resist Wafer image is opposite of mask image Exposed resist hardens and is insoluble Developer removes unexposed resist Positive Resist Mask image is same as wafer image Exposed resist softens and is soluble Developer removes exposed resist Resolution Issues Clear Field Versus Dark Field Masks

30 30 The Purpose of Photoresist in Wafer Fab To transfer the mask pattern to the photoresist on the top layer of the wafer surface To protect the underlying material during subsequent processing, e.g., etch or ion implantation.

31 31 Ten steps of Photolithography UV Light HMDS Resist Mask λ λ 1-3) Vapor prime 4) Spin coat 5) Soft bake 6) Alignment and Exposure 7) Post-exposure bake (PEB) 8) Develop 9) Hard bake 10) Develop inspect Figure 13.9 Quirk & Serda (modified)

32 32 Automated Wafer track for Photolithography Load station Vapor prime Resist coat Develop and rinse Edge-bead removal Transfer station Wafer stepper (Alignment/Exposure system) Wafer Transfer System Soft bake Cool plate Cool plate Hard bake Figure Quirk & Serda

33 33 Photolithography Track System Photo courtesy of Advanced Micro Devices, TEL Track Mark VIII Photo 13.2 Quirk and Serda

34 34 Thank You