CMOS Scaling Beyond FinFETs: Nanowires and TFETs

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SEMATECH Symposium June 23, 2011 Tokyo Accelerating the next

TFETs Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and

International SEMATECH Manufacturing Initiative, ISMI, Advanced

1 SEMATECH Symposium June 23, 2011 Tokyo Accelerating the next technology revolution CMOS Scaling Beyond FinFETs: Nanowires and TFETs Chris Hobbs, Wei-Yip Loh, Kerem Akarvardar, Paul Kirsch, and Raj Jammy June 22, 2010 Copyright 2009 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

2 Outline Advanced CMOS Scaling Overview Nanowires TFETs Summary 14 June

3 Device scaling options I d,sat V g 14 June

4 Device scaling options I d,sat V g 14 June

5 Device scaling options 1 Very high mobility/high injection velocity Ge, Ge, InGaAs Graphene [ e ~15000 cm 2 /V-s at RT] I d,sat V g 14 June

6 Device scaling options 2 1 Very high mobility/high injection velocity Ge, Ge, InGaAs Graphene [ e ~15000 cm 2 /V-s at RT] I d,sat Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET V g 14 June

7 Why are Multi-Gates beneficial? ngle Gate Device Source Gate Channel Extension Halo Gate can t control down here, so drain leaks to source Well Conventional MOSFET Scaling to improve performance Drain Source Source and drain are much closer Gate looses control of channel region Thin silicon channel with gate on both sides helps maintain channel control. Lg Drain Double Gate Device Source Gates on both sides Thin licon Channel Drain Gate Wafer Surface Fin Source FinFET Drain 4-Gate Device Gate Source Nanowire Drain 14 June

8 Performance and power tradeoff Typical Ion-Ioff for CMOSFETs Same transistor with specifications tuned for performance or cost. 14 June

9 Performance and power tradeoff Typical Ion-Ioff for CMOSFETs All Face Transistor Scaling Issues (need new materials/architectures/novel processes) Same transistor with specifications tuned for performance or cost. 14 June

10 MOSFET scaling trends Planar New materials -Ge Device III-V Device 12nm+ 45nm High-K 32nm 22nm? 16nm? SEMATECH, VLSI 2009 Intel, IEDM 2007,9 SEMATECH, IEDM 2010 (Production) Intel IEDM (Production) Intel IEDM 2009 Past: Performance improved by scaling device dimensions. Now: Performance improved by Novel Materials and Architectures. Planar CMOS and Beyond: A continuous spectrum of devices. IBM, IEDM Non planar Intel Tri-Gate, VLSI nm Length B. Doris IEDM 2002 NXP FINFET, VLSI 2007 SEMATECH, IEDM 2009 Nano-wire (LETI IEDM 08) 14 June

11 Non-planar devices Motivation: Gate wrap-around helps control short channel effects in scaled devices High mobility channels enables higher drive currents Scaling Pathways w and w/o 3 rd gate? OR High Bulk vs SOI Heterogeneous High OR Homgeneous N HM HfO 2 TiN BOX 14 June

Critical FinFET/Trigate/Nanowire Modules

Processing and integration Group IV channel

module issues are similar to FinFET module

12 Critical FinFET/Trigate/Nanowire Modules Source/Drain SEG, doping and silicide Gate etch Fin Scaling and smoothness Source/Drain SEG, doping and silicide Gate etch NW Scaling and smoothness Ge Ge Ge Ge Processing and integration Group IV channel material Spacer etch and process schemes FinFET/Trigate Processing and integration Group IV channel material BOX Spacer etch and process schemes Nanowire Most nanowire module issues are similar to FinFET module issues with added degree of integration complexity. 14 June

50 mv NFET Gate length = 40 nm NW width =

13 licon Nanowires W mask = 50 nm source suspended wires 450 nm drain MG HiK 10 nm ngle Nanowire licide Data V D = 1 V W mask = 50 nm 450 nm I D (A/um) PFET V D = 50 mv NFET Gate length = 40 nm NW width = 50 nm NW height = 20 nm V GS (V) 14 June

14 Gate wraparound improves rolloff DIBL (V/V) Swing (V/dec) V DS = -50 mv BOX Lmask (nm) Omega Gate FinFET N HM HfO 2 TiN PFET PFET Nanowire device has smaller rolloff compared to FinFET. Wrapping gate around channel improves short channel control. Long channel SS is similar for Omega-Gate and FinFET. Vdd scaling limited by SS. Different device structure needed to reduce Vdd. TFET! Gate-All-Around (GAA) Device: Total current in nanowire limited by crossectional area. Multiple GAA nanowires to meet ITRS targets. In contrast, total current in FinFET can be increased with taller fins. 14 June

NWs Pt N Ge Ge 200 nm BOX BOX Ge Ge Stacking nanowires helps

15 Stacked nanowire formation using Ge Ge/ Superlattice Fin etch Selective Ge etch Ge Ge BOX Ge Ge BOX Ge Ge Suspended NWs Pt N Ge Ge 200 nm BOX BOX Ge Ge Stacking nanowires helps increase total drive current to meet ITRS targets. 14 June

High mobility Ge FinFETs/nanowires eff (cm 2 /V-s)

Ge {100}<100> {110}<110> {100}<100> (100) universal

8nm) 0 0 1x10 13 2x10 13 N INV (#/cm 3 ) shell/core

2nm) Universal (100) Extracted by Split CV Method Ge

16 High mobility Ge FinFETs/nanowires eff (cm 2 /V-s) (110) (100) Ge {110}<110> Ge {100}<100> {110}<110> {100}<100> (100) universal Ge fin (Tinv= 1.8nm) 0 0 1x x10 13 N INV (#/cm 3 ) shell/core fin (Tinv=1.5nm) fin (Tinv = 1.2nm) Universal (100) Extracted by Split CV Method Ge PFETs have higher mobility than fins. Potential for performance > strained in non-planar devices 14 June

17 Outline Advanced CMOS Scaling Overview Nanowires TFETs Summary 14 June

18 Device scaling options 2 1 Very high mobility/high injection velocity Ge, Ge, InGaAs Graphene [ e ~15000 cm 2 /V-s at RT] I d,sat V g Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET Improve on-off ratio Tunnel FET Very steep SS << 60 mv/dec Low bias voltages (<< 1V) Nano Electro Mechanical switch (NEMS) Hybrid: I on by CMOS + I off by NEMS Zero Leakage Power 14 June

19 Device scaling options 2 1 Very high mobility/high injection velocity Ge, Ge, InGaAs Graphene [ e ~15000 cm 2 /V-s at RT] I d,sat 3 V g Better electrostatic control Multiple gates + more channel area FinFETs, nanowire FET Improve on-off ratio Tunnel FET Very steep SS << 60 mv/dec Low bias voltages (<< 1V) Nano Electro Mechanical switch (NEMS) Hybrid: I on by CMOS + I off by NEMS Zero Leakage Power 14 June

20 V CC scaling for green electronics Power Density (W/cm 2 ) 1E+03 Active Power Density 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 Passive Power Density 1E-04 1E Gate Length (μm) (B. Meyerson et al.,, IBM, Semico Conf., 2004) (P. Packan (Intel), 2007 IEDM Short Course) Passive power has shown continuous increase due to V DD scaling limit. V CC scaling limited by V T and subthreshold slope (which is kt/q limited) need green devices not governed by kt/q ~ 60mV/dec limit. 14 June

21 Working mechanism of TFET Log I D Log I D Low I ON MOSFET High I OFF Operation Range TFET Energy [ev] Cox q exp( V ) GS C C kt Band-to-Band Tunneling, SS < 60mV/dec E c E v I DS ON C OX C DEP ox OFF V G dep φ S E C E V X [nm] MOSFET: For Narrow On/Off Voltage Range: Low Ioff Low Ion High Ion High Ioff Electrons go over thermionic energy barrier Boltzmann distribution of carriers causes leakage. TFET: Carriers go through the energy barrier. 14 June

PIN tunneling FETs I D [A/um] 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 46mV/dec 10-14 -2.0-1.5-1.0-0.5 0.

22 PIN tunneling FETs I D [A/um] mV/dec V G [V] 5x10-6 4x10-6 3x10-6 2x10-6 1x10-6 V G =-2.0V V G =-1.5V V G =-1.0V V D [V] Several types TFETs with PIN, Metal Schottky PIN and -pocket PIN have been demonstrated. Ultra-low subthreshold of < 50 mv/dec has been achieved over 10 3 order of drive current. SEMATECH-UCB DARPA STEEP Project Very Low SS, need more Ion. 14 June

23 N D activation for high I on TFET SEMATECH-UCB ESSDERC 2010 Ni n+ L g = 56nm Metal gate 80nm N spacer p+ High-K Ni I D (A/ m) 10-3 Experimental m. Overlap 10nm 10-4 m. Overlap 5nm m. Overlap 0nm Highest I on (~ 109 A/ m) at Vcc = 1.0V for TFET using optimized flash anneal for N d activation. Good Ion, poor SS. [1] IEDM Tech. Dig. 2009, p.949. [2] IEDM Tech. Dig. 2008, p [3] IEDM Tech. Dig. 2008, p [4] IEEE Trans, ED., vol 51(2), p. 279, [5] IEEE EDL, vol. 28(8), p. 743, [6] 40th ESSDERC 2010, p V gate -V BT (V) I drain (A/ m) L g ~ 46 nm V g = 0V I Thermonic I Tunnel Temp = 213K~313K in step of 20K V ds (V) Channel SS (mv/dec) Ion 1 References V ds (V) Ion/Ioff 1 RT ( A/ m) S. Mookerjea [1] InGaAs 150~ > 10 3 T. Krishnamohan [2] Ge 50 ~ T. Krishnamohan [2] > 10 2 F. Mayer [3] Ge > > 10 2 F. Mayer [3] 42 ~ K. K. Bhuwalka [4] W. Y. Choi [5] * This work [6] 120 ~ > > Ion is taken at overdrive of V g -V BT = 2.0V except for *. Ioff taken at onset of BT-BT, V BT 14 June

E g engineering : H-TFET Effective E g can be engineered by using heterostructure (e.g. Ge on ) Ge % from 25 ~ 50% Bandgap engineering to enhance tunneling Abrupt doping gradient by in-situ B- doped

24 E g engineering : H-TFET Effective E g can be engineered by using heterostructure (e.g. Ge on ) Ge % from 25 ~ 50% Bandgap engineering to enhance tunneling Abrupt doping gradient by in-situ B- doped Ge and post annealing n+ (Drain) Gate i- p+ge (Source) Heterostructure TFET Ec offset and bandgap narrowing for high tunneling g g g g SEMATECH-UCB DARPA Joint Project Much lighter Hole mass 14 June

25 III-V tunnel FETs 1E-03 Drain Current (A/µm) 1E-06 1E-09 (InAs) Eg=0.36eV, Vd=0.2V (Ge) Eg=0.69eV, Vd=0.5V () Eg=1.1eV, Vd=1V Gate Voltage (V) [C. Hu et al, VLSI-TSA, pp.14-15, 2008] D it (#/cm 2 /ev High Dit In 0.53 GaAs CB edge VB edge p-type n-type V gate (V) I diode (A/cm 2 ) Junction Leakage n+i-p+ In 0.53 GaAs Diodes 1st lot 2nd lot V diode (V) Tunneling is a strong function of bandgap. III-V has smaller bandgap and heterostructures (e.g. InAs/Al x Ga 1-x Sb) have staggered or even zero bandgap direct tunneling. Preliminary InGaAs TFETs results indicates further optimization is needed to improve the poor SS, high I off, high Dit and poor R co. 14 June

26 Novel design: pocket structure TFET P+ Pocket N+ Source P+ Drain P- Buried Oxide [ C. Hu et al, VLSI-TSA, April, 2008 ] Large field, good capacitive coupling btw gate & pocket Abrupt turn-on due to overlap of valence/conduction bands Tunable turn-on voltage 14 June

Dopant-segregated -pocket TFET SEMATECH-UCB VLSI Symp. 2010 Achieved sub-60 mv/dec (46mV/dec) with 30% dies showing sub- 60mV/dec TFET with high-k/mg 100nm Ni BOX Ni Gate N+ BOX Probability 0.9 0.8 0.

27 Dopant-segregated -pocket TFET SEMATECH-UCB VLSI Symp Achieved sub-60 mv/dec (46mV/dec) with 30% dies showing sub- 60mV/dec TFET with high-k/mg 100nm Ni BOX Ni Gate N+ BOX Probability Schottky-Source 0.1 P-I-N licon TFET Subthreshold Swing [mv/dec] I D [A/ m] Measured m. w/ pocket m. no pocket Ni Ni V G [V] Gate BOX N+ < Pocket > Gate BOX N+ < No Pocket > 14 June

28 PVCR I drain (A/ m S-MLD pocket InGaAs pocket TFETs V g -V BT = 0.2 V to 1.5 V in step of 0.1 V L g = 100 nm K Control pocket Control V gate (V) Pocket V drain (V) D it (#/cm 2 /ev VB edge p-type Control Pocket CB edge V gate (V) n-type P++ P+ i AlO x N+ TFET with pocket n+ Tunneling Front P++ P+ N+ N+/p- pocket structure achieved on InGaAs TFET. Enhanced drive current obtained due to enhanced vertical field at gated pocket n-p+ junction. Improved gate coupling and Dit observed. AlO x Control TFET i 14 June

29 I drain (A/ m mulation of TFETs Ge/ pocket [1] Ge pocket [1] IV TFETs (mulation) s-ge/s- [2] pocket [1] Ge UTB [4] 60 mv/dec PNPN [5] Intel 32nm LP IEDM 2009 [9] Ge-source NW [3] Ge NW [3] TFET Ge TFET MOSFET V gate (V) NW [3] I drain (A/ m IIIV TFETs (mulation) SG Pocket 10-3 E g =0.36 [1] GaSb-InAs UTB [7] GaSb-InAs NW [7] InSb UTB [7] InSb NW [7] 60 mv/dece g = 0.17 ev Intel 32nm LP IEDM 2009 [9] InAs NW [6] E g = 0.37 ev V gate (V) [1] C. Hu et al. (invited), VLSI-TSA 2008 [2] O.M. Nayfeh et al., EDL, 1074, [3] A.S. Verhulst et al., APL, 104, , [4] Q. Zhang et al., Solid-State Elect. 30, [5] V. Nagavarapu et al., TED, 1013, [6] M. Luisier et al., EDL, 602, [7] M. Luisier et al., IEDM, 913, [8] S. Mookerjea et al., IEDM, 949, InGaAs [8] E g = 0.72 ev 14 June

30 Current TFET performance I drain (A/ m P-TFET (experimental) 32nm pfet [9] (LP) DSS TFET [17] L g = 20 m 60 mv/dec 10-9 SOI TFET [14] L g = 100 nm V gate (V) p-channel TFET [16] L g = 56 nm I drain (A/ m N-TFET (experimental) n-channel TFET[12] Lg = 70nm 60 mv/dec Ge-source TFET [15] L g = 5 m In 0.7 GaAs In 0.53 GaAs TFET [13] TFET [8] L g = 100nm L g = 100nm V gate (V) PNPN TFET [5] L g = 1 m Experiments show higher sub-threshold slope than simulations. 32nm nfet No physical demonstration of TFET with both high Ion > 100 A/ m and SS < 60 mv/dec has been demonstrated so far. GeOI TFET [14] L g = 0.4 m 14 June

31 Summary Power Constrained CMOS Scaling requires new materials and device structures to enable continued scaling. Nanowires: Better short channel control than FinFETs with added degree of integration complexity TFETs: Band to band tunneling transport mechanism allows for sub- 60mV subthreshold slope Vcc reduction lower power consumption TFETs simulations show promise for Vcc reduction and additional process improvements are needed to improve device performance. 14 June

III-V on Si for VLSI. 200 mm III-V on Si. Accelerating the next technology revolution. III-V nfet on 200 mm Si

III-V on Si for VLSI. 200 mm III-V on Si. Accelerating the next technology revolution. III-V nfet on 200 mm Si III-V on Si for VLSI Accelerating the next technology revolution 200 mm III-V on Si III-V nfet on 200 mm Si R. Hill, C. Park, J. Barnett, J. Huang, N. Goel, J. Oh, W.Y. Loh, J. Price, P. Kirsch, P, Majhi,