Nanoscale III-V CMOS

Transcription

1 Nanoscale III-V CMOS J. A. del Alamo Microsystems Technology Laboratories Massachusetts Institute of Technology SEMI Advanced Semiconductor Manufacturing Conference Saratoga Springs, NY; May 16-19, 2016 Acknowledgements: Students and collaborators: D. Antoniadis, J. Lin, W. Lu, A. Vardi, X. Zhao Sponsors: Applied Materials, DTRA, KIST, Lam Research, Northrop Grumman, NSF, Samsung Labs at MIT: MTL, EBL

2 Contents 1. Motivation: Moore s Law and MOSFET scaling 2. Planar InGaAs MOSFETs 3. InGaAs FinFETs 4. Nanowire InGaAs MOSFETs 5. InGaSb p-type MOSFETs 6. Conclusions 2

3 1. Moore s Law at 50: the end in sight? 3

4 Moore s Law Moore s Law = exponential increase in transistor density Intel microprocessors 4

5 Moore s Law How far can Si support Moore s Law?? 5

6 Transistor scaling Voltage scaling Performance suffers Supply voltage: Transistor current density: Intel microprocessors Intel microprocessors Transistor performance saturated in recent years 6

7 Chip Price vs. Chip Cost Chip area price: Chip area cost: Intel microprocessors Holt, ISSCC 2016 Increasing chip cost might bring the end to Moore s Law 7

8 8

9 Moore s Law: it s all about MOSFET scaling 1. New device structures: Enhanced gate control improved scalability 9

10 Moore s Law: it s all about MOSFET scaling 2. New materials: n-channel: Si Strained Si SiGe InGaAs p-channel: Si Strained Si SiGe Ge InGaSb Future CMOS might involve: two different channel materials with two different relaxed lattice constants! del Alamo, Nature 2011 (updated) 10

11 III-V electronics in your pocket! 11

12 2. Self-aligned Planar InGaAs MOSFETs dry-etched recess selective MOCVD W Mo Lin, IEDM 2012, 2013, 2014 Lee, EDL 2014; Huang, IEDM 2014 implanted Si + selective epi reacted NiInAs Sun, IEDM 2013, 2014 Chang, IEDM

13 Self-aligned Planar InGaAs MIT W Mo Recess-gate process: CMOS-compatible Refractory ohmic contacts (W/Mo) Extensive use of RIE Lin, IEDM 2012, 2013,

14 Fabrication process Mo/W ohmic contact + SiO 2 hardmask SF 6, CF 4 anisotropic RIE Resist CF 4 :O 2 isotropic RIE SiO 2 W/Mo n + InGaAs/InP InGaAs/InAs InAlAs -Si InP Waldron, IEDM 2007 Cl 2 :N 2 anisotropic RIE Digital etch Finished device O 2 plasma H 2 SO 4 Pad Mo HfO 2 Lin, EDL 2014 Ohmic contact first, gate last Precise control of vertical (~1 nm), lateral (~5 nm) dimensions MOS interface exposed late in process 14

15 Mo Nanoscale Contacts Mo on n + -In 0.53 Ga 0.47 As: R c ~ 40 Ω.μm for L c ~ 20 nm Need low c and m Mo best contact system Average c = m 2 Lu, EDL

16 L g =20 nm InGaAs MOSFET I d (ma/ m) 1.0 L g =20 nm R on =224 m V gs -V t = 0.5 V 0.4 V V ds (V) Lin, IEDM 2013 L g = 20 nm, L access = 15 nm MOSFET tightest III-V MOSFET made at the time 16

17 Highest performance InGaAs MOSFET Channel: In 0.7 Ga 0.3 As/InAs/In 0.7 Ga 0.3 As Gate oxide: HfO 2 (2.5 nm, EOT~ 0.5 nm) 3.45 ms/ m L g =70 nm: Record g m,max = 3.45 ms/ m at V ds = 0.5 V R on = 190 m Lin, EDL

18 Benchmarking: g m in MOSFETs vs. HEMTs g m of InGaAs MOSFETs vs. HEMTs (any V DD, any L g ): MIT MOSFETs del Alamo, J-EDS 2016 InGaAs MOSFETs now superior to InGaAs HEMTs No sign of stalling more progress ahead! 18

19 Excess OFF-state current Transistor fails to turn off: I d (A/ m) 10-5 L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) OFF-state current enhanced with V ds Band-to-Band Tunneling (BTBT) or Gate-Induced Drain Leakage (GIDL) Lin, IEDM

20 Excess OFF-state current I d (A/ m) T=200 K V ds =0.7 V L g =80 nm 120 nm 280 nm 500 nm V gs -V t (V) Lin, EDL 2014 Lin, TED 2015 L g OFF-state current additional bipolar gain effect due to floating body I d (A/ m) I d (A/ m) 10-5 L g =500 nm w/ W/ BTBT+BJT w/o W/O BTBT+BJT L g =500 nm V ds V ds =0.3~0.7 V step=50 mv V gs (V) Simulations V ds =0.3~0.7 V step=50 mv V gs (V) 20

21 Planar MOSFET scaling limit Scaling of linear subthreshold swing del Alamo, J-EDS 2016 ideal scaling λ =electrostatic scaling length Nearly ideal electrostatic scaling behavior At limit of scaling around L g ~50 nm 21

22 3. InGaAs FinFETs Intel Si Trigate MOSFETs 22

23 Bottom-up InGaAs FinFETs Aspect-Ratio Trapping Fiorenza, ECST 2010 Si Epi-grown fin inside trench Waldron, VLSI Tech

24 Top-down InGaAs FinFETs Radosavljevic, IEDM 2010 dry-etched fins 60 nm Kim, IEDM

25 InGaAs FinFETs: g m g m per width of gate periphery Kim, IEDM 2013 Natarajan, IEDM 2014 Oxland, EDL 2016 g m [ms/ m] Si FinFETs InGaAs FinFETs W f [nm] channel aspect ratio Narrowest InGaAs FinFET fin: W f =25 nm Best fin aspect ratio of InGaAs FinFET: 1 g m much lower than planar InGaAs MOSFETs Radosavljevic, IEDM 2011 Thathachary, VLSI

26 InGaAs MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Sub-10 nm fin width Aspect ratio > 20 Vertical sidewalls Vardi, DRC 2014, EDL 2015, IEDM

27 InGaAs Double-Gate MOSFET Vardi, VLSI 2016 CMOS compatible process Mo contact-first process Fin mask left in place double-gate MOSFET 27

28 InGaAs Double-Gate MOSFET L g =30 nm, W f =17 nm, H c =40 nm (AR=2.3): I d [ma/ m] 1.0 L g =30 nm V GS =0.75 V W 0.8 f =17 nm 0.6 V GS =0.25 V V V DS [V] I d [A m] 1E-3 V DS =500 mv 1E-4 50 mv 1E-5 S sat =140 mv/dec 1E-6 DIBL=220 mv/v 1E-7 L g =30 nm W f =17 nm 1E V GS [V] g m =1.12 ms/µm R on =230 Ω.µm S sat =140 mv/dec Vardi, VLSI

29 InGaAs FinFETs: g m benchmarking g m per width of gate periphery g m [ms/ m] Si FinFETs MIT InGaAs FinFETs InGaAs FinFETs W f [nm] First InGaAs FinFETs with W f <10 nm First InGaAs FinFETs with channel aspect ratio >1 29

30 InGaAs FinFETs: g m benchmarking Figure-of-merit for density: g m per fin width g m /W f [ms/ m] MIT InGaAs FinFETs 5.7 Si FinFETs InGaAs FinFETs W f [nm] Improved by 50% over earlier InGaAs FinFETs Still far below Si FinFETs poor sidewall charge control 30

31 InGaAs FinFETs: electrostatics Linear subthreshold swing scaling: del Alamo, J-EDS 2016 ideal scaling λ c =electrostatic scaling length Close to ideal scaling reveals good quality sidewalls 31

32 Impact of fin width on V T InGaAs doped-channel FinFETs: 50 nm thick, N D ~10 18 cm -3 Oxide: Al 2 O 3 /HfO 2 (EOT~3 nm) Strong V T sensitivity for W f < 10 nm; much worse than Si Due to quantum effects Vardi, IEDM

33 4. Nanowire InGaAs MOSFETs Waldron, EDL 2014 Tanaka, APEX 2010 Persson, EDL 2012 Tomioka, Nature 2012 Nanowire MOSFET: ultimate scalable transistor Vertical NW: uncouples footprint scaling from L g and L c scaling 33

34 InGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Vapor-Solid-Liquid (VLS) Technique Selective-Area Epitaxy Riel, MRS Bull 2014 Björk, JCG

35 InGaAs VNW-MOSFETs fabricated via top-down MIT Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : cm 3 Si doping Top-down approach: flexible and manufacturable Zhao, IEDM

36 Key enabling technologies: RIE + digital etch RIE = BCl 3 /SiCl 4 /Ar chemistry Digital Etch (DE) = self-limiting O 2 plasma oxidation + H 2 SO 4 oxide removal RIE + 5 cycles DE Sub-20 nm NW diameter DE shrinks NW diameter by 2 nm per cycle Aspect ratio > 10 Smooth sidewalls Zhao, EDL

37 Optimized RIE + Digital Etch 15 nm 240 nm Zhao, EDL 2014 Sub-20 nm resolution Aspect ratio = 16, vertical sidewall Smooth sidewall and surface 37

38 Tomioka, Nature 2012 Persson, DRC 2012 Process flow 38

39 NW-MOSFET I-V characteristics: D=40 nm I d A/ m) 350 V gs =-0.2 V to 0.7 V in 0.1 V step 300 Bottom electrode as the source (BES) V ds (V) Single nanowire MOSFET: L ch = 80 nm 3 nm Al 2 O 3 (EOT = 1.5 nm) g m,pk =620 V DS =0.5 V R on =895 Ω.μm Zhao, EDL 2016 (submitted) g m,pk ( S/ m) I d (A/ m) V gs (V) V ds=0.5 V V ds =0.5 V V ds =0.05 V S=98 mv/dec, V ds =0.05 V S=110 mv/dec, V ds =0.5 V DIBL = 177 mv/v V gs (V) 39

40 This work Zhao, 2016 (submitted) Best bottom up devices Berg, IEDM 2015 Vertical InGaAs NW-MOSFETs Benchmark g m,pk ( S/ m) V ds =0.5 V Tanaka, APEX 2010 Tomioka, IEDM 2011 Tomioka, Nature 2012 Persson, DRC 2012 Persson, EDL 2010 Zhao, IEDM 2013 Berg, IEDM 2015 This work S sat (mv/dec) Top down approach as good as bottom up approach 40

41 InGaAs VNW MOSFETs: electrostatics Linear subthreshold swing scaling: del Alamo, J-EDS 2016 ideal scaling λ c =electrostatic scaling length Close to ideal scaling reveals good quality sidewalls 41

42 5. InGaSb p type MOSFETs Planar InGaSb MOSFET demonstrations: Nainani, IEDM 2010 Takei, Nano Lett

43 InGaSb p type FinFETs at MIT Key enabling technology: BCl 3 /N 2 RIE [digital etch under development] 20 nm fins, 20 nm spacing Lu, IEDM nm fins, AR>13 Smallest W f = 15 nm Aspect ratio >10 Fin angle > 85 Dense fin patterns 43

44 Si-compatible contacts to p + -InAs Ni/Ti/Pt/Al on p + -InAs (circular TLMs): Lu, IEDM 2015 Record ρ c : 3.5x10-8 Ω.cm 2 at 400 o C 44

45 InGaSb FinFETs Fin mask left in place double-gate MOSFET Channel: 10 nm In 0.27 Ga 0.73 Sb Gate oxide: 4 nm Al 2 O 3 (EOT=1.8 nm) Gate: 45 nm Mo Lu, IEDM

46 InGaSb FinFETs Lu, IEDM 2015 W f = nm L g = μm N f = 70 46

47 InGaSb FinFET I-V characteristics L g = 100 nm, W f = 30 nm (AR=0.33) Normalized by conducting gate periphery Lu, IEDM 2015 High current Poor turn-off 47

48 Peak g m at T=290K: g m benchmarking Lu, IEDM 2015 g m ( S/ m) 100 This work (FinFET) In 0.27 Ga 0.73 Sb Planar MOSFETs Yuan, 2013 [7] Nainani, 2010 [8] Chu, 2014 [11] Xu, 2011 [12] Nagaiah, 2011 [13] GaSb GaSb In 0.36 Ga 0.64 Sb L g ( m) In 0.35 Ga 0.65 Sb In 0.2 Ga 0.8 Sb First InGaSb FinFET Peak g m approaches best InGaSb planar MOSFETs 48

49 Conclusions 1. Great recent progress on planar, fin and nanowire III-V MOSFETs 2. Planar and multigate InGaAs MOSFETs exhibit nearly ideal electrostatic scaling behavior 3. Device performance still lacking for multigate designs 4. P-type InGaSb MOSFETs promising 49

50 A lot of work ahead but exciting future for III-V electronics 50