InGaAs Nanoelectronics: from THz to CMOS

Transcription

1 InGaAs Nanoelectronics: from THz to CMOS J. A. del Alamo Microsystems Technology Laboratories, MIT IEEE International Conference on Electron Devices and Solid-State Circuits Hong Kong, June 3, 2013 Acknowledgements: D. Antoniadis, A. Guo, D.-H. Kim, T.-W. Kim, D. Jin, J. Lin, N. Waldron, L. Xia Sponsors: Intel, FCRP-MSD Labs at MIT: MTL, NSL, SEBL 1

2 Outline 1. InGaAs HEMT today 2. InGaAs HEMTs towards THz operation 3. InGaAs MOSFETs: towards sub-10 nm CMOS 2

3 A bit of perspective Invention of AlGaAs/GaAs HEMT: Fujitsu Labs First InAlAs/InGaAs HEMT on InP: Bell Labs First AlGaAs/InGaAs Pseudomorphic HEMT: U. Illinois 1985 Main attraction of InGaAs: RT μ e = 6,000~30,000 cm 2 /V.s Mimura JJAPL 1980 Chen EDL 1982 Ketterson EDL

4 InGaAs Electronics Today UMTS-LTE PA module Chow, MTT-S Gb/s modulator driver 77 GHz transceiver Carroll, MTT-S 2002 Tessmann, GaAs IC 1999 Bipolar/E-D PHEMT process Single-chip WLAN MMIC, Morkner, RFIC 2007 Henderson, Mantech

5 InGaAs High Electron Mobility Transistor (HEMT) Modulation doping: 2-Dimensional Electron Gas at InAlAs/InGaAs interface 5

6 InGaAs HEMT: high-frequency record vs. time f T (GHz) Teledyne/MIT: f T =688 GHz, f max =800 GHz on InP substrate on GaAs substrate Year f T =710 GHz f max =478 GHz Chang APEX 2013 (NCTU) Devices fabricated at MIT Highest f T of any FET on any material system Best balanced f T and f max of any transistor on any material 6

7 InGaAs HEMTs: circuit demonstrations 10-stage 670 GHz LNA 80 Gb/s multiplexer IC Leong, IPRM 2012 Single-stage 500 GHz LNA Wurfl, GAAS 2004 Sarkozy, IPRM 2013 Tessmann, CSIC

8 InGaAs HEMTs on InP used to map infant universe WMAP=Wilkinson Microwave Anisotropy Probe Launched 2001 Full-sky map of Cosmic Microwave Background radiation (oldest light in Universe) age of Universe: 13.73B years (±1%) µm InGaAs HEMT LNA Pospieszalski MTT-S

9 A closer look: InGaAs HEMTs at MIT Kim, EDL QW channel (t ch = 10 nm): InAs core InGaAs cladding e = 13,200 cm 2 /V-sec - InAlAs barrier (t ins = 4 nm) - L g = 30 nm 9

10 L g =30 nm InGaAs HEMT V GS = I D [ma/ m] V 0.2 V 0 V U g H 21 Kim, EDL g m [ms/ m] V DS [V] Gains [db] MSG/MAG K 1 0 K V DS = 0.5 V V GS [V] V DS =0.5 V, V GS =0.2 V Frequency [Hz] High transconductance: g m = 1.9 ms/μm at V DD =0.5 V First transistor of any kind with both f T and f max > 640 GHz 10

11 How to reach f t = 1 THz? THz 30% reduction in all the parasitics 600 f T [GHz] 400 V DS = 0.6 V Measured f T 200 Modeled f T Model Projection 30 L g [nm] 100 Kim, IEDM 2011 f T = 1 THz feasible by: scaling to L g 25 nm ~30% parasitic reduction 11

12 Record f T InGaAs HEMTs: megatrends x=0.53 Over time: L g, In x Ga 1-x As channel x InAs L g, x InAs saturated no more progress possible? 12

13 Record f T InGaAs HEMTs: megatrends Over time: t ch, t ins t ch, t ins saturated no more progress possible? 13

14 Limit to HEMT barrier scaling: gate leakage current InGaAs HEMTs L g =40 nm V DS =0.5 V Kim, EDL 2013 At L g =30-40 nm, modern HEMTs are at the limit of scaling! 14

15 Solution: MOS gate! InGaAs HEMTs 10-5 x! L g =40 nm V DS =0.5 V Al 2 O 3 (3 nm)/inp (2 nm)/ingaas MOSFET Kim, EDL 2013 Need high-k gate dielectric: HEMT MOSFET! 15

16 InGaAs MOSFETs with f T =370 GHz (Teledyne/MIT/IntelliEpi/Sematech) Kim, APL H 21 Gains [db] U g MSG f T = 370 GHz f max = 280 GHz V DS =0.5 V Frequency [Hz] Channel: 10 nm In 0.7 Ga 0.3 As Barrier: 1 nm InP + 2 nm Al 2 O 3 L g = 60 nm g m = 2 ms/μm R ON = 220 Ω.μm 16

17 III-V MOSFET: a >30 year pursuit! GaAs Kohn, EL 1977 GaAs Mimura, EL 1978 Poor electrical characteristics due to oxide/semiconductor interface defects Fermi level pinning 17

18 Recent breakthrough: oxide/iii-v interfaces with unpinned Fermi level In-situ UHV Ga 2 O 3 -Gd 2 O 3 on GaAs Ex-situ ALD Al 2 O 3 on GaAs Ren, SSE 1997 Ye, EDL

19 Self-cleaning during ALD ALD eliminates surface oxides that pin Fermi level: First observed with Al 2 O 3, then with other high-k dielectrics First seen in GaAs, then in other III-Vs Huang, APL 2005 Clean, smooth interface without surface oxides 19

20 Interface quality: Al 2 O 3 /InGaAs vs. Al 2 O 3 /Si Al 2 O 3 /Si Al 2 O 3 /InGaAs E v E c E v E c Werner, JAP 2011 Brammertz, APL 2009 Close to conduction band edge, Al 2 O 3 /InGaAs shows comparable interface state density to Al 2 O 3 /Si interface 20

21 Electron injection velocity: InGaAs vs. Si Measurements of electron injection velocity in HEMTs: E C v inj E V Kim, IEDM 2009 Liu, Springer 2010 Khakifirooz, TED 2008 del Alamo, Nature 2011 v inj (InGaAs) increases with InAs fraction in channel v inj (InGaAs) > 2v inj (Si) at less than half V DD ~100% ballistic transport at L g ~30 nm 21

22 InGaAs n-mosfet: best candidate for post-si CMOS Si CMOS scaling seriously stressed Moore s law threatened? Intel microprocessors 22

23 The III-V view 23

24 The III-V view The Si view 24

25 CMOS scaling in the 21 st century Si CMOS has entered era of power-constrained scaling : Microprocessor power density saturated at ~100 W/cm 2 Pop, Nano Res 2010 Future scaling demands V DD 25

26 How to enable further V DD reduction? Transistor is switch: Goals of scaling: reduce transistor footprint reduce V DD extract maximum I ON for given I OFF The path forward: increase electron velocity I ON tighten electron confinement S use InGaAs! 26

27 L g =30 nm InGaAs HEMT Subthreshold characteristics Kim, EDL V DS = 0.5 V 10-5 I D V DS = 0.05 V I D, I G [A/ m] V DS = 0.5 V 10-8 I G 10-9 V DS = 0.05 V V GS [V] S = 74 mv/dec Sharp subthreshold behavior due to tight electron confinement in quantum well 27

28 L g =30 nm InGaAs HEMT Subthreshold characteristics Kim, EDL I ON =0.52 ma/μm V DS = 0.5 V 10-5 I D V DS = 0.05 V I D, I G [A/ m] I OFF =100 na/μm V DS = 0.5 V 10-8 I G 10-9 V DS = 0.05 V V GS [V] 0.5 V S = 74 mv/dec At I OFF =100 na/μm and V DD =0.5 V, I ON =0.52 ma/μm 28

29 InGaAs HEMTs: Benchmarking with Si FOM that integrates short-channel effects and transport: I I OFF =100 na/µm, V DD =0.5 V Kim EDL 2010 InGaAs HEMT (MIT) IEDM 2008 InGaAs HEMTs: higher I ON for same I OFF than Si 29

30 III-V MOSFET: possible designs n + n + Recessed S/D QW-MOSFET Regrown S/D QW-MOSFET Trigate MOSFET Nanowire MOSFET 30

31 Self-Aligned InGaAs QW-MOSFETs (MIT) Scaled barrier (InP: 1 nm + HfO 2 : 2 nm) 10 nm thick channel with InAs core Tight S/D spacing (L side ~30 nm) Process designed to be compatible with Si fab Lin, IEDM 2012 L side 31

32 L g =30 nm Self-aligned QW-MOSFET At V DS = 0.5 V: g m = 1.4 ms/µm S = 114 mv/dec R ON = 470 m I D (A/ m) Lin, IEDM 2012 L g =30 nm V DS =0.5 V 50 mv V GS (V) S (mv/dec) 32

33 Scaling and benchmarking I on ( A/ m) I off =100 na/ m V DD =0.5 V III-V FETs MIT HEMT Planar Trigate This work L g (nm) S min (mv/dec) Lin, IEDM III-V FETs V DS = 0.5 V L g (nm) MIT HEMT Planar Trigate This work Superior behavior to any planar III-V MOSFET to date Matches performance of Intel s InGaAs Trigate MOSFETs [Radosavljevic, IEDM 2011] 33

34 Long-channel InGaAs MOSFET Barrier: InP (1 nm) + Al 2 O 3 (0.4 nm) + HfO 2 (2 nm) Lin, IEDM 2012 S = 69 mv/dec at V DS = 50 mv Close to lowest S reported in any III-V MOSFET: 66 mv/dec [Radosavljevic, IEDM 2011] 34

35 Regrown source/drain InGaAs QW-MOSFET on Si (HKUST) Zhou, IEDM 2012 MOCVD epi growth on Si wafer n + -InGaAs raised source/drain Self-aligned to gate Composite barrier: InAlAs (10 nm) + Al 2 O 3 (4.6 nm) 35

36 Characteristics of Lg=30 nm MOSFET At VDS=0.5 V: gm = 1.7 ms/µm S = 186 mv/dec RON = 157 Ω.µm Zhou, IEDM

37 Multiple-gate MOSFETs # gates improved electrostatics enhanced scalability FinFET Trigate Nanowire Chen, ICSICT

38 InGaAs Trigate MOSFET (Intel) Radosavljevic, IEDM 2011 H FIN =40 nm Improved subthreshold swing as fin is made thinner 38

39 InGaAs Nanowire MOSFET (Purdue) 30x30 nm fin L ch = 50 nm Barrier: 10 nm Al 2 O 3 # wires = 4 Gu, IEDM 2011 Gu, APL 2011 Gu, EDL 2012 I on = 720 μa/μm (86 μa/wire) g m = 0.51 ms/μm (61 μs/wire) S = 150 mv/dec 39

40 Conclusions: exciting future for InGaAs Most promising material for ultra-high frequency and ultra-high speed applications first THz transistor? Most promising material for n-mosfet in a post- Si CMOS logic technology first sub-10 nm CMOS logic? InGaAs + Si integration: THz + CMOS + optics integrated systems? 40