Device architectures for the 5nm technology node and beyond Nadine Collaert

Transcription

1 Device architectures for the 5nm technology node and beyond Nadine Collaert Distinguished member of technical staff, imec

2 Outline Introduction Beyond FinFET: lateral nanowires and vertical transistors High mobility materials New switching mechanisms Summary

3 Introduction

4 The future heterogeneous system MAXIMIZING FUNCTIONALITY AND REDUCING POWER DENSITY BGA Memory stack Many-core Logic chip I/O chip Heterogeneous Devices on the same die Chip cooling Optical I/O 3D-TSV Smart Silicon interposer

5 Standard CMOS, beyond Si & Beyond CMOS High bandgap MX2 materials Spin logic... Low bandgap high mobility materials Vertical devices FinFET, GAA,... Standard CMOS and new devices to enable future heterogeneous systems Ability to innovate & co-integrate devices to optimize performance & functionality is key

6 Log (Functional CPU Scaling) Increase compute power SYSTEM Advanced power management Interposer 3D SiC 5nm 3nm 3D SoC 3D Logic 7nm DESIGN DEVICE 9T 7.5T 14nm 20nm FinFET 10nm 6T GAA MTJ CFET VFET MX2 SPIN TFET MATERIALS 28nm HKMG Co v Ch-SiGe Ru Ch-IIIV v LITHOGRAPHY 193i (Multi)-Patterning EUV Year of 1 st Production

7 Beyond FinFET

8 Dynamic power [ W] Power-performance scaling: FinFET scaling to 7nm nm 9T FinFET 10nm 9T FinFET 0.8V V nm 0.9V > 40% < 30% > 20% < 15% 0.7V 10nm 7.5T FinFET 0.75V 7nm 7.5T FinFET RO INVD1 FO3 50 CGP BEOL load psige(50%), nsi 0.65V 0.55V 0.45V 0.50V 0.50V Performance [GHz]

9 Scaling down the fin width to improve electrostatics Fin width FW 5 nm 7 nm 10 nm 15 nm FH TSMC16 HP (ulvt) TSMC16 SVT For a target gate length of 14nm, fin width has to be reduced to 5nm to meet device electrostatics.

10 From FinFET to lateral nanowires (NW) Fin width FW 5 nm 7 nm 10 nm 15 nm FH D NH D= 10nm, V dd =0.7V TSMC16 HP (ulvt) D= 7nm, V dd =0.5V TSMC16 SVT Nanowire FETs provide better electrostatics at relaxed nanowire diameter.

11 10nm 30nm 30nm 25nm 30nm 30nm 5nm 5nm 10nm 5nm From FinFET to lateral NW Fin 1 wire 2 wires 3 wires SiO 2 0.5nm Decrease Sswing & DIBL Fin HfO 2 1.5nm NW spacin g 5nm Roundin g radius 2.5nm Fin Increase R access Spacin g 5nm STI STI STI STI Higher stack is needed for nanowire FETs to compensate smaller cross section than FinFET. Increased parasitics require the enabling of new features e.g. internal spacers

12 Dynamic power [ W] Power-performance scaling: from FinFET to lateral NW nm 0.9V 14nm 9T FinFET 10nm 9T FinFET 0.8V 0.75V 10nm 7.5T FinFET 0.75V 7nm 7.5T NanoWire 0.7V RO INVD1 FO3 50 CGP BEOL load psige(50%), nsi 0.65V 0.45V 0.45V 0.55V 0.50V 0.50V 0.45V Performance [GHz] >50% +30% 5nm 7.5T NanoWire 0.65V 5nm 6T NanoWire 0.65V NW device allows further voltage scaling and performance gains

13 Lateral NW: an evolutionary path from FinFET H. Mertens et al., VLSI Symp (a) Si/SiGe Multi-stack (b) Fin patterning & STI (c) Dummy gate (d) Spacer, S/D, ILD0 & Gate removal (e) SiGe or Si removal (f) Final gate stack

14 Demonstration of a 2-stacked lateral nanowire device H. Mertens et al., VLSI Symp No stressors WF metal 45nm Si NW RMG-HK 8 nm Demonstrated 2-stacked Si NWFET Improved performance and electrostatics as compared to FinFETs

15 Going vertical Integration Device Circuit System InGaAs W top contact Gate Si

16 High mobility materials

17 Carrier Mobility (cm 2 /Vs) Why high mobility materials? Graphene 400x After R. Pillarisetty, Nature, InSb InAs 10-40x Ge 2-6x Si GaAs InP V dd limited < 0.5V? Energy Band Gap (ev) New Materials with Major Transport Enhancement over Si

18 Challenges for high mobility materials Fin Replacement/Wide field/srb Epi & Integration Junction engineering & contacting InGaAs Gate stack & Surface Passivation Defect & Phys. Metrology Device performance and scalability

19 Challenges for epitaxial growth Global Wafer-level Stress-Relaxed Buffer Local Wide-Area Virtual Substrate (Wide-Trench ART) Local Device-level Virtual Substrate (Narrow Trench ART) Defect layer InP 500 nm Si Defect layer 300mm 0.5 m-500nm < 50nm

20 20 Ge FinFET using fin replacement technique FIN PITCH DOWN TO 45NM L. Witters et al., VLSI Symp nm

21 Gm sat [ S/ m] High performance III-V devices on 300mm Si Q=30 300mm GAA Q=20 V DD =0.5V Rectangles: InAs Triangles: InGaAs Q=10 N. Waldron et al., IEDM, X. Zhou et al., VLSI QW FF FinFET 300mm GAA IIIVoI 500 vertical NW IIIVoI CELO SS sat [mv/dev] 300mm FinFET Q=5

22 Need for co-integration with Si Leakage Power N7 Si FinFET V dd = 0.7V 25% 29% N10 Si FinFET V dd =0.8V IIIV/Ge V dd = 0.7V Si-Ge-IIIV Co-integrated? High mobility channels offer more performance but leakage span limited Need Si-channel co-integration for SOC

23 What about 2D materials? Advantages: Expected reduced SCE No dangling bonds Large choice of materials and bandgaps Challenges: Large scale growth of MX2 Choice of MX2 material for NFET and PFET Gate stack Contacts

24 Heterogeneous integration with base CMOS 3-D Hetero-SOC Cu Interconnect (T~400 o C) Sequentially Processed Can the 2-D crystals be selectively grown between the interconnects? Or by transfer & bond? 2-D Crystal Devices Cu Interconnect (T~400 o C) Base CMOS Thermal budget of 2-D device processing is typically low-t, but material growth is still unclear

25 New switching mechanisms

26 Moving to tunnel FET ULTRA-LOW VOLTAGE APPLICATIONS

27 BTBT generation (cm -3 s -1 ) 27 From group IV to III-V BTBT Generation Rate (GR) InGaAs53 (dir) [1] Ge (dir) Ge (ind) Si (ind) <110> direction Electric field (MV/cm) Probability of tunneling is dependent on bandgap Si dir Ge dir SiGe30 dir Higher tunneling SiGe50 dirgeneration rate for low bandgap SiGe80 materials dir InGaAs dir Si ind Increased Ge performance ind expected for III-V SiGe30 ind SiGe50 ind SiGe80 ind Kao et al, TED 59(2), 292 (2012) & [1] Q. Smets et al, SSDM 2013

28 I d (ua/um) I on I off = 100 pa/µm III-V homojunction n-tfet process and device A. Alian et al., IEDM, Vd= 200 mv 70% 53% 53%-shifted V g (V) Dewey et al., p. 45, VLSI 2012 [11] [8] [4] [6] Noguchi et al [10] Tomioka et al., p.47, VLSI, 2012 homo-junction hetero-junction This work [7] [5] SS min [mv/dec] Significant boost with 8nm strained InGaAs (70% In) (quantum confinement & bandgap) Very low TAT observed SS less degraded by D it in TFET due to energy range for carrier exchange in TFET operations

29 III-V Heterostructures Staggered and broken gap configurations Si InAs GaSb GaAs Ge GaP InP InSb E c GaAsSb In 0.53 Ga 0.47 As E v InGaAs GaSb 0.5 As 0.5 a(a)= Substrate % Lattice InP mismatch 4% Lattice mismatch S. El Kazzi et al., EUROMBE A. Verhulst et al., IEDM, Sb-based materials needed to allow best trade-off between performance & electrostatics

30 From 3D TFET to 2D TFET After Eli Yablonovitch 2012, UC Berkeley 3D-3D 2D-2D Soft Transition Abrupt Transition Steepness of the swing over a wide-vg range limited by 3-D DOS Investigate 2-D TFET options

31 2-D TFETS with 2-D MX 2 (TMD) heterostructures DFT V G V S MoS 2 V G 0 V HfS 2 Left Device model electrode V D doped e /cm 2 High-k intrinsi c High-k Broken gap devices with large bandgaps 2nm Lattice mismatch is no longer an issue van der Waals stacking Right electrod e doped e /cm 2 31

32 Negative capacitance FET (NC-FET) SS= VGS s s (logid) = m x n S. Salahuddin et al., Nano letters, V G C FE s C S Sub 60mV/dec due to negative capacitance of a ferroelectric oxide based gate stack (m < 1) Tunable hysteresis behavior: non-volatile circuits and noise immune logic

33 Spin logic Spin based devices offer different Energy-Delay tradeoffs Spin torque majority gate D. Nikonov et al., IEEE EDL, Spin wave devices

34 Summary

35 Summary Need for more energy-efficient Core Logic Devices and specialty devices Lateral NW is a natural evolution from FinFET and will enable to continue scaling beyond 7nm due to improved electrostatics VFET offers 30-40% SRAM area benefit: 1 st step towards vertical logic? Scaling of supply voltage is required to address power crisis and higher mobility channels are needed to increase performance at reduced V DD New switching mechanisms like TFET, NCFET and spin logic being considered for ultra-low power applications