Sub-30 nm InAs Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO 2 Insulator

Transcription

1 Sub-30 nm InAs Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO 2 Insulator Jianqiang Lin, Dimitri A. Antoniadis, and Jesús A. del Alamo Microsystems Technology Laboratories, MIT December 12, 2012 Sponsors: FCRP-MSD Center, Intel Corp.

2 tivation Superior electron transport properties in InAs and InGaAs material systems ~10X mobility vs. Silicon Extraordinary electron velocity [J. del Alamo, Nature 2011] I d-sat = Q i_xo x v inj InAs HEMTs V inj Strained Si V DS =0.5 V Si V DS = V 2

3 Goal: Self-aligned III-V QW-MOSFETs L side n + n + Footprint Deeply scaled channel and barrier Architecture: Self-aligned contact Process integration: towards Si-MOS-compatible processes and materials 3

4 Device fabrication n + cap InP substrate Sputtered contact CVD hard mask Mesa isolation 4

5 Device fabrication n + cap InP substrate Resist n + cap InP substrate Sputtered contact CVD hard mask Mesa isolation Gate lithography Gate recess by RIE / 5

6 Device fabrication n + cap InP substrate Resist n + cap InP substrate n+ n + cap cap Sputtered contact CVD hard mask Mesa isolation Gate lithography Gate recess by RIE / Damage annealing * Cap wet etch; pulled-in Digital etching of InP * [Lin, APEX 2012] 6

7 Device fabrication n + cap InP substrate Resist n + cap InP substrate Sputtered contact CVD hard mask Mesa isolation Gate lithography Gate recess by RIE / Damage annealing n+ n + cap cap G ALD n+ n + cap cap Cap wet etch; pulled-in Digital thinning of InP ALD gate dielectric deposition gate evaporation Gate head photo and pattern Pad formation 7

8 n + cap InP substrate n+ n + cap cap ALD Device fabrication Resist n + cap InP substrate n+ n + cap cap Sputtered contact CVD hard mask Mesa isolation Gate lithography Gate recess by RIE / Damage annealing Cap wet etch; pulled-in Digital thinning of InP ALD gate dielectric deposition gate evaporation Gate head photo and pattern Self-aligned Au-free (Front-end) Pad formation InP exposed last Lift-off free (Front-end) Low thermal budget 8

9 QW-MOSFET: L g =30 nm (S/D) Cap 30 nm (G) HfO 2 /InP (total t ch =10 nm): 2 nm InAs clad by 3 and 5 nm In 0.7 Ga 0.3 As InP barrier thinned by digital etch Barrier InP =1 nm, HfO 2 =2 nm [including barrier: EOT~ 0.8 nm] Low- : t,s/d =30 nm, R sh =5 / 9 Contact to gate spacing = 20~30 nm

10 QW-MOSFET: L g =30 nm I D ( A/ m) L g = 30 nm V GS = 0.5 V 0.4 V I D ( A/ m) L g =30 nm V DS =0.5 V 50 mv g m ( S/ m) V DS (V) -0.2 V V GS (V) g m,max = 1.4 ms/ m at V DS =0.5 V L g =30 nm (S/D) Little hysteresis (< 10 mv) Cap (G) R on =470. m, R sd =450. m L side HfO (mainly attributed to L side ) 2 /InP 10

11 QW-MOSFET: L g =30 nm subthreshold characteristic I D (A/ m) L g =30 nm V DS =0.5 V S (mv/dec) mv V GS (V) S min =114 mv/dec at V DS =0.5 V, DIBL=230 mv/v Nearly constant S throughout subthreshold region I g <1 na/µm over entire voltage range 11

12 Scaling and benchmarking: ON current I on ( A/ m) I off =100 na/ m V DD =0.5 V MIT HEMT Planar Trigate This work Definition of I on L g (nm) III-V FETs Superior behavior to any planar III-V MOSFET to date Matches performance of III-V Trigate MOSFETs [Radosavljevic, IEDM 2011] 12

13 Scaling and benchmarking: Subthreshold swing and V t roll-off S min (mv/dec) 160 III-V FETs S min at V DS = 0.5 V MIT HEMT Planar Trigate This work L g (nm) V t (V) V =V at t GS I D =1 A/ m, V DS =0.5 V MIT HEMT This work L g (nm) S min superior to all planar III-V MOSFETs to date Matches III-V Trigate MOSFET [Radosavljevic, IEDM 2011] V t roll-off starts at L g ~50 nm 13

14 DIBL DIBL (mv/v) MIT HEMT This work L g (nm) DIBL= 230 mv/v for L g =30 nm Related to residual RIE damage and the heterostructure 14

15 QW-MOSFET: L g =22 nm 22 nm I D ( A/ m) L g = 22 nm V GS = 0.5 V 0.4 V Functional device with L g =22 nm g m, max = 1.1 ms/µm at V DS =0.5 V I D ( A/ m) -0.5 V V DS (V) L g =22 nm 300 V DS =0.5V mv V GS (V) g m ( S/ m)

16 Dielectric/barrier scaling Long-channel In 0.53 Ga 0.47 As QW-MOSFET Gate HfO 2 (2 nm) Al 2 O 3 (0.4 nm) (1 nm) In 0.53 Ga 0.47 As (15 nm) Cross section: Intrinsic portion of the device I D (A/ m) V DS =0.5 and 0.05 V L g = 300 m S min =69 mv/dec V GS (V) Fresh InP surface exposed right before high-k deposition Al 2 O 3 (0.4 nm) + HfO 2 (2 nm) [EOT of deposited insulator layer ~0.6 nm] InP thinned to ~ 1 nm [Gate- EOT~0.9 nm] 16

17 Benchmarking: Long-channel subthreshold swing on planar MOSFETs S min (mv/dec) D it =10 13 /cm 2 ev 1 III-V FETs MIT HEMT MOSFET This work EOT of dielectric (nm) qdi Smin 60(1 t ) mv/dec C ox EOT of dielectric refers to the deposited insulating layer Close to lowest S min reported in any III-V MOSFET: 66 mv/dec [EOT=1.2 nm] [Radosavljevic, IEDM 2011] 17

18 HfO 2 vs. Al 2 O 3 Recent study at U. Texas at Dallas: HfO 2 on InP yields lower D it than Al 2 O 3 D it (x10 12 cm -2 ev -1 ) 500 C PDA 100 HfO 2 10 Al 2 O 3 E V InGaAs E C E-E i (ev) D it (x10 12 cm -2 ev -1 ) C PDA Al 2 O 3 HfO 2 E V InP E C E-Ei (ev) [R. Galatage, R.M.Wallace, E.M.Vogel - UT Dallas] 18

19 HfO 2 vs. Al 2 O 3 C ( F/cm 2 ) Gate HfO 2 (2 nm) (1 nm) (10 nm) 50 k to 1.4 MHz HfO 2 (2 nm) V g (V) C ( F/cm 2 ) Gate Al 2 O 3 (2 nm) (1 nm) (10 nm) 50 k to 1.4 MHz Al 2 O 3 (2 nm) V g (V) Split C-V measurement on L g = 20 m Lower dispersion for HfO 2 below threshold 19

20 HfO 2 vs. Al 2 O 3 I D (A/ m) L g =150 nm V DS =0.5 V S min =95 mv/dec HfO 2 (2 nm) Al 2 O 3 /HfO 2 (0.4/2 nm) V GS (V) S (mv/dec) HfO 2 (2 nm) Al 2 O 3 /HfO 2 (0.4/2 nm) V DS =0.5 V, L g =150 nm I D (A/ m) First demonstration of HfO 2 directly on InP for InAs QW-MOSFET Steeper subthreshold swing at L g =150 nm at low V GS Lower EOT 20

21 bility in Long QW-MOSFETs e (cm 2 V -1 S -1 ) HfO 2 (2 nm) Al 2 O 3 (2 nm) N s (x10 12 cm -2 ) 4650 cm 2 V -1 s -1 at N s =4x10 12 cm -2 L g =20 m bility extracted by split C-V method Gate High-k (1 nm) (10 nm) : InGaAs/InAs/InGaAs (3/2/5 nm) N s not corrected by D it design beneficial to maintain high mobility: Undoped channel InAs-rich channel Buried-channel design 21

22 Conclusions Novel self-aligned gate-last MOSFET architecture: Self-aligned gate to contact metals (L side ~20-30 nm) Improved Si-MOS process compatibility Fresh InP surface exposed right before high-k deposition Deeply scaled dielectric Outstanding performance and short-channel effects in devices with L g =30 nm Demonstrated subthreshold swing of 69 mv/dec and mobility of 4650 cm 2 V -1 s -1 at N s =4x10 12 cm -2 in long channel QW-MOSFETs HfO 2 / InP dielectric for superior performance 22

23 Acknowledgement Fabrication facility at MIT labs: MTL, NSL, SEBL. Heterostructure grown by IntelliEPI Inc. MIT collaborators: L. Xia, D. Jin, A. Guo, X. Zhao, S. Warnock, L. Guo, J. Hoyt, J, Teherani, W. Chern. MSD collaborators: R. Galatage, R. M. Wallace, E. M. Vogel. Industrial collaborators: T.-W. Kim (Sematech), D.-H. Kim (Global Foundries), J.-M. Kuo (IntelliEPI). 23

24 Thank you. 24