Scaling Electronics: Kelin J. Kuhn Intel Fellow. Kelin Kuhn / MIT / April 4 th

Transcription

1 Scaling Electronics: Trends and Bottlenecks Kelin J. Kuhn Intel Fellow Director of Advanced Device Technology 1

2 Moore s Law Scaling of the SRAM Bitcell Area ( m 2 ) X bitcell area scaling 90nm 65nm 45nm 32nm Process generation 22nm 2

3 Impact of Process Enhancers um) current (ma/u Drive S. Natarajan, IEDM 2008 S. Natarajan, IEDM

4 III-V MO OBILITY Source Gate n-ge Ge Drain System-in-package STRUCTURE Strain System-on-chip 32nm UTB SOI Fins Wires/Ribbons ELECTROSTATIC Kelin Kuhn / MIT / April 4CONFINEMENT th 2011

5 III-V MO OBILITY Source Gate n-ge Ge Drain System-in-package STRUCTURE Strain System-on-chip 32nm UTB SOI Fins Wires/Ribbons ELECTROSTATIC Kelin Kuhn / MIT / April 4CONFINEMENT th 2011

6 Transistor Performance Trend Drive Current (ma/um) V, 100 na I OFF 90nm 130nm 65nm 45nm 32nm Strain Hi-k-MG Other Classic scaling PMOS Gate Pitch (nm) 100 Strain is a critical ingredient in modern transistor scaling Strain was first introduced at 90nm, and its contribution has increased in each subsequent generation 6

7 Strain in modern devices Stress memorization Wei, VLSI 2007 Mayuzumi, IEDM 2007 Ghani, IEDM 2003 Yang, IEDM 2008 Auth, VLSI 2008

8 ORIENTATION (100) surface top down (110) surface top down <110> <100> (100) <110> <110> Standard wafer / direction (100) Surface / <110> channel (100) Surface / <100> (a 45 degree wafer) Both <110> directions are the same. <100> Non-standard <111> (110) Surface (110) <110> Three possible channel directions <110> <111> and <100> <100>

9 ORIENTATION (100) surface top down (110) surface top down (100) <110> <100> <110> Standard wafer / direction (100) Surface / <110> channel (100) Surface / <100> (a 45 degree wafer) Both <110> directions are the same. (110) <100> <111> <110> Non-standard (110) Surface <110> <100> (100) BEST NMOS (110) <110> BEST PMOS Three possible channel directions <110> <111> and <100> Yang Yang AMD/IBM EDST EDST

10 Orientation and Strain: More complex for non-(100) orientations Modified from Thompson IEDM

11 Si vs Ge MOSFETs Gate Source Source n-ge Drain Intel 45nm HiK-MG Si device Intel HiK-MG Ge device The introduction of manufacturable HiK-MG transistors has led to the reconsideration of Ge channels 12

12 The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. Challenge of Lattice Mismatch Issues Device Layer Silicon Direct Deposition Defects Si Silicon Dislocations III-V Stacking faults Si Twin Defects Adapted from J. Kavalieros VLSI SC

13 Ge and PMOS Bandgap and Electron Affinity (ev) Hole and Electron Mobility (cm2-v.s) 0 1 Si Ge InP GaAs InSb Ge mobility makes it uniquely interesting for PMOS K. Kuhn ECS

14 Low Field Long Channel Mobility (as a function of stress) 1000 Si (110) Si cm^2/vs Mobility (100) Si 200 Hole Stress (GPa) K. Kuhn ECS

15 Low Field Long Channel Mobility (as a function of stress) Si (100) Ge (110) Si Ge (110) Ge Mobility cm^2/vs (100) Si 200 Hole Stress (GPa) K. Kuhn ECS

16 Bandg gap and Ele ectron Affin nity (ev) Ge Historical Issues: Still critical today Si Ge InP GaAs InSb MO (cm2/v V.s) Si (no strain) Ge 100% Ge 55% SiGe 25% TOXE (A) Narrow Bandgap Poor Quality Dielectric K. Kuhn ECS

17 Narrow Bandgap Ene ergy Bandga ap (ev) Eg SiGe (PERCENTAGE) mobility (cm m^2/v.s) Hole s [A/um] Id, I Source 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 Adapted from Saraswat [59], Krishnamohan [60] BTBT h e DRAIN DRAIN High Junction Leakage Eg Drain 1.E-08 Source Source 1.E Vg - Vt [V] Band-to-band tunneling: challenge for low Eg materials K. Kuhn ECS

18 Narrow Bandgap Adapted from Saraswat [59], Krishnamohan [60] Source High BTBT Weak quantum confinement Narrow effective energy gap Source h e Eg Drain Reduced BTBT Strong quantum confinement Wide effective energy gap h e Eg Drain Two solutions: Use lower voltages and/or use quantum confined systems K. Kuhn ECS

19 Bandg gap and Ele ectron Affin nity (ev) Ge Historical Issues: Still critical today Si Ge InP GaAs InSb MO (cm2/v V.s) Si (no strain) Ge 100% Ge 55% SiGe 25% TOXE (A) Narrow Bandgap Poor Quality Dielectric K. Kuhn ECS

20 Dielectric Quality Ge to GeO (110) 2 Ge/Ge GeO 2 sub oxide transition Ge(111) Heynes, 2008 [9] Since HiK-MG dielectrics typically form with a bilayer (the HiK + an interface layer) the challenge of germanium oxide still exists. Germanium oxide exists in several morphologies, unfortunately, most are hydroscopic and/or volatile. K. Kuhn ECS

21 Ge Dielectric: One strategy: Use an Si passivation layer Zimmerman IEDM 2006 Si passivation Hellings EDL 2009 Si passivation Mitard VLSI 2009 Si passivation 22

22 Ge Dielectric: Another strategy: Advanced GeO 2 processing Ge diffusion High-pressure O2 (HPO) suppresses surface reaction Low-T oxygen Annealing (LOA) Kita IEDM 2009 HPO + LOA Lee IEDM 2009 HPO + LOA Kuzum TED 2009 GeOxNy + LOA 23

23 Ge Benchmarking Yamamoto 2007 Wang 2007 Ioff (A/u um) Irisawa E-03 1.E-04 1.E-05 1.E-06 1.E-07 1E08 1.E-08 Romanjek 2008 Nicholas 2007 Batail 2009 Zimmerman 2006 Tezuka 2006 Andrieu E Liao 2008 Ion (ma/um) Harris 2007 Mitard 2009 Hellings 2009 Batail [2009] updated 24

24 III-V vs Ge: NMOS The Lure of High Mobility d y (ev) ndgap and n Affinity Ban Electro Si Ge InP GaAs InSb ron V.s) nd Electr ty (cm2-v Hole an Mobili Adapted from J. Kavalieros - VLSI SC 2007 K. Kuhn ECS

25 Low m* MOSFETs: Density-of-states states bottleneck On-current of a MOSFET I Q Velocity υ Diffusive : mobility μ, υ = μe Ballistic: injection velocity υ inj Light m* high μ, high υ inj From R. Kim Charge Q MOS limit (C Q» C ox ), C C ox Light m* less D (C Q ), less C, less Q More important for thin oxide (large C ox ), DOS bottleneck Q C V V G C C C C Q ox 2 q D Q th 26

26 T. Kelin Skotnicki, Kuhn / MIT IEDM / April th SC

27 Success of III-V Materials as Transistor sto Channel (Vcc = 0.5V) LECTRON MO OBILITY [cm 2 /V Vs] E Silicon InSb * InGaAs >30X improvement x x10 13 SHEET CARRIER DENSITY [cm -2 ] >5X R. Chau, Intel, ESSDERC 2008 At Vcc ~ 0.5V III-V n-channel devices show significantly higher mobility (30X) and higher effective velocity (5X) than strained silicon MOSFETs 28

28 Significant Gain in Intrinsic Drive Over Si at Low Vcc (e.g. 0.5V) Measurement Data 55% rrent, I (ma/ / m) D Drain cu Experiment & Simulation 80nm InGaAs QW, T OXE =27A R SD matched to Si (Simulated) 80nm InGaAs QW T OXE =34A 2X R SD 40nm Strained Si 20% 0.1 T OXE =14A V -V =0.3V G T Drain voltage, V (V) DS 80% R. Chau, ESSDERC 2008 At a gate overdrive = 0.3V, III-V QWFET shows 55% intrinsic drive current gain over strained Si At a drain voltage of 0.5V, III-V QWFET shows >20% I DSAT gain over strained Si (despite thicker Toxe and higher R SD) 29

29 5 High-Current L & -L channels: 5 Approaches Rodwell et al, 2010 Device Research Conference 6/21/2010 Rodwell, DRC, 2010 blue=occupied red=vacant ed drive current K 1 normaliz only InGaAs EET=Equivalent Electrostatic Thickness =T / +T / ox SiO2 ox inversion SiO2 semiconductor Si 0.4 nm 0.6 nm EET=1.0 nm g=2 g=1 0 includes the wavefunction depth term T inversion SiO2 / semiconductor m*/m o normalize ed drive current K nm EET=1.0 nm 0.3 nm 0.4 nm EET=Equivalent Electrostatic Thickness =T ox SiO2 / ox +T inversion SiO2 / semiconductor g=2, m /m =0.7 perpendicular 0 g=2, m /m =0.6 perpendicular 0 g=2, m perpendicular /m 0 =0.5 ma V 1 84 gs V J K th m 1V 3/ Kelin Kuhn / MIT / April 4 th m*/m o Drain cu urrent, ma/ m nm well pitch 0.3 nm EET 0.6 nm EET 6 5 V -V =0.3 V gs th nm well pitch 2 EET=Equivalent Electrostatic Thickness 1 =T / +T / ox SiO2 ox inversion SiO2 semiconductor 0 includes the wavefunction depth term T / inversion SiO2 semiconductor m*/mo

30 Use of L-valleys: GaAs From R. Kim GaAs 4 nm (100) k y [001] 8 L-valleys [011] Small DOS with high v inj High DOS with low v inj k x [010] single band from Γ k y [-1-12] [-211] Multiple bands from More DOS with high v inj Γ and L (111) k x [-110] 31

31 III-V MO OBILITY Source Gate n-ge Ge Drain System-in-package STRUCTURE Strain System-on-chip 32nm UTB SOI Fins Wires/Ribbons ELECTROSTATIC Kelin Kuhn / MIT / April 4CONFINEMENT th 2011

32 III-V MO OBILITY Source Gate n-ge Ge Drain System-in-package STRUCTURE Strain System-on-chip 32nm UTB SOI Fins Wires/Ribbons ELECTROSTATIC Kelin Kuhn / MIT / April 4CONFINEMENT th 2011

33 Ultra-thin body with RSD Extension of planar technology (less disruptive to manufacturing) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Potential for body bias

34 Ultra-thin body with RSD Capacitance (Increased fringe to contact/facet) Rext: (Xj/Tsi limitations) Challenges Variation: (film thickness changes affects VT and DIBL) Strain: (strain transfer from S/D into the channel) Manufacturing: (requires both thin Tsi and thin BOX) Performance: (transport challenges with thin Tsi)

35 Body Bias with Thin BOX T. Skotnicki IEDM SC

36 Barral IEDM 2007 Ultra-thin body Cheng VLSI 2009 / IEDM 2009 Lg=25nm Tsi=6nm 37

37 Barral IEDM 2007 Ultra-thin body Cheng IEDM 2009 Lg=25nm 38

38 TriGate WIDTH = 2H + W WIDTH LENGTH 39

39 Nomenclature FINFET TRIGATE -GATE BOX block chan nnel gate Silicon -FET GAA 40

40 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal subthreshold slope (gates tied together) Improved RDF (low doped channel) Can be on bulk or SOI Excellent channel control

41 MuGFET with RSD Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal subthreshold slope (gates tied together) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control

42 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Possibility for independent gate operation Improved RDF (low doped channel) Excellent channel control

43 MuGFET Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring Hsi/Wsi/epi) Challenges Gate wraparound (Endcap coverage) Small fin pitch (2 generation scale?) Fin/gate fidelity on 3 D (Patterning/etch) Fin Strain engr. (Effective strain transfer from a fin into the channel) Rext: (Xj/Wsi limitations) Topology (Polish / etch challenges) 44

44 Chang IEDM 2009 MuGFET Wu IEDM 2010 Lg=25nm 45

45 Nanowire Benefits Nearly ideal subthreshold slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Excellent channel control

46 Nanowire Benefits Nearly ideal subthreshold slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control

47 Nanowire Integrated wire fabrication (Epitaxy? Other?) Mobility degradation (scattering) Gate conformality (dielectric and metal) Wire stability (bending/warping) Challenges Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring a myriad of new sources) Fin Strain engr. (Effective strain transfer from wire into the channel) Rext: (Xj/Wsi limitations) Fin/gate fidelity on 3 D (Patterning/etch) Topology (Polish / etch challenges) 48

48 Dupre IEDM 2008 Nanowire FETs Bangsaruntip - IEDM

49 Hashemi/Hoyt IEDM 2008 EDL/ESSDRC 2009 Nanowire FETs Moselund IEDM

50 III-V MO OBILITY Source Gate n-ge Ge Drain System-in-package STRUCTURE Strain System-on-chip 32nm UTB SOI Fins Wires/Ribbons ELECTROSTATIC Kelin Kuhn / MIT / April 4CONFINEMENT th 2011

51 III-V MO OBILITY Source Gate n-ge Ge Drain System-in-package STRUCTURE Strain System-on-chip 32nm UTB SOI Fins Wires/Ribbons ELECTROSTATIC Kelin Kuhn / MIT / April 4CONFINEMENT th 2011

52 System Integration Discrete ICs 2-D Integration (SoC) M. Bohr Stanford D Integration Logic Memory Power Reg. Radio Sensors Photonics System integration needed for performance, power, form factor Challenge is to integrate wider range of heterogeneous elements 53

53 The Vision of RF SOC Antennas Front End RFIC (RFCMOS Module (III-V) /BiCMOS) Baseband Switches/PA VCO (PHY)/MAC Filters LNA T/R Switch PA LNA RX Mixer RF Synth ADC DAC PLL TX Mixer (RF Front End) (RF IC) (MAC/BB) MAC/Base eband Apps Proc cessor Full integration of RF components into monolithic silicon chips C.-H. Jan IEDM 2010

54 32 nm SoC Process Features Logic Transistor I/O Trans Voltage Metal Passives Embedded Memory High Performance 1.2V Low Power 9 Layer High Perf Resistor High Dense SRAM Std Performance 1.8V Thick Gate 7-12 Layer Dense Capacitor Low Voltage SRAM Low Power 3.3V Thick Gate High Q Inductor High Speed SRAM M. Bohr Stanford 2011 Intel s 32 nm SoC process Illustrates the breadth of an SoC feature set 55

55 CMOS: A critical platform for for RF SoC integration Cut t-off freq quency f T (GHz) C. Jan IEDM 2010 Intel 90nm Intel 32nm Intel 45nm Intel 65nm ITRS 2007 ITRS / L g (nm -1 ) CMOS competitive with III-V for some applications, 32nm peak f T ~ 445 GHz Kelin C.-H. Kuhn Jan / MIT / April IEDM 4 th

56 CMOS: A critical platform for for RF SoC integration /um 2 vg*w*l(v 2 /Hz z) S v 1E-10 C. Jan IEDM E-11 1E E nm 90nm 65nm 45nm 32nm 1E Frequency (Hz) S Svg W L g id K W L 1 2 f 2 m Cox 10x 1/f flicker noise improvement on five nodes Benefits from Cox scaling enabled by high-k Critical for phase noise and other mixed signal designs Flicker noise not degraded by HiK/MG Transition Kelin C.-H. Kuhn Jan / MIT / April IEDM 4 th

57 SOC and Interconnect 0.13 um 6 layers Polymer 4.5 um TM1 (Thick Metal) Cu 32 nm 8 layers M1 M8 Interconnects Thick metal improves the quality of RF passives C.-H. Jan IEDM

58 Inductors Enabled by Thick Metal Power Combiner Single End Inductor Differential Inductor Balun Transformer/Splitter Kelin Kuhn / MIT / April 4th 2011 C.-H. Jan IEDM

59 Vertical Architectures Vertical orientation may enable new circuit concepts Benefits 50% reduction in plan view density Possibility for different N/P materials/orientations Reduced vertical interconnect capacitance

60 Vertical Architectures Rext: (Xj/Wsi limitations) it ti Fin/gate fidelity on 3 D (Patterning/etch) Topology (Polish / etch challenges) Gate conformality (dielectric and metal) Challenges Thermal processing (Top layer may need to be processed over existing bottom layer) Contacts (Diffusion-diffusion, Gate-gate contacts extremely challenging) Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring a myriad of new sources) Lithography (May double the number of FE critical layers) Strain engineering (more challenging than single layer)

61 3D NAND Deck-by-Deck - Planar NAND + SOI Vertical NAND - Vertical Pillar with Surround Gate Structure K-T Park, et al. Solid State Ckt 2009 H.Tanaka, et al. VLSI Tech Dig 2007 Two categories of 3 D NAND: Deck by Deck and Vertical 62

62 Batude IEDM 2009 stacked 110/100 Vertical Jung IEEE TED D stacked 6T 63

63 System-in-Package 3 D Chip Stacking BENEFITS: High density chip-chip p connections Small form factor Combines dissimilar technologies CHALLENGES: Added cost Degraded power delivery, heat sinking Area impact on lower chip Package Top Chip TSV Bottom Chip Package CPU TSV Memory M. Bohr Stanford D chip stacking using through-silicon vias 64

64 Limit to visibility remains ~ decade TECHNOLOGY GENERATION 45nm nm nm nm nm nm 2017 Beyond 2020 MANUFACTURING DEVELOPMENT RESEARCH Carbon Nanotube ~1nm diameter QW III-V Device 5nm Not to scale Nanowire 10 atoms across Graphene 1 atom thick

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