InGaAs MOSFETs for CMOS:

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1 InGaAs MOSFETs for CMOS: Recent Advances in Process Technology J. A. del Alamo, D. Antoniadis, A. Guo, D.-H. Kim 1, T.-W. Kim 2, J. Lin, W. Lu, A. Vardi and X. Zhao Microsystems Technology Laboratories, MIT 1 Global Foundries 2 Sematech International Electron Devices Meeting 2013 Washington D.C., December 9, 2013 Acknowledgements: Sponsors: Intel, FCRP-MSD, Sematech, NSF, SMA, MIT-Technion Labs at MIT: MTL, NSL, SEBL 1

2 InGaAs High Electron Mobility Transistors g m =2.7 ms/μm Kim, IEDM 2011 InGaAs channel InAlAs barrier Main attractions of InGaAs: μ e = 6,000-30,000 cm 2 300K v inj = x K 2

3 InGaAs MOSFETs g m =2.7 ms/μm Lin, IEDM 2013 InGaAs channel High-K oxide * *inversion-mode Extraordinary recent progress of InGaAs MOSFETs 3

4 Technology issue #1: MOS gate stack Challenge: metal/high-k oxide gate stack Fabricated through ex-situ process Very thin barrier (EOT ~ 0.5 nm) Low gate leakage (I G <1 A/cm 2 at V GS =0.5 V) Low D it (<3x10 12 ev -1.cm -2 in top ~0.3 ev of bandgap and inside CB) Reliable high-k dielectric n + n + 4

5 Interface quality: Al 2 O 3 /InGaAs vs. Al 2 O 3 /Si Al 2 O 3 /Si Al 2 O 3 /InGaAs E v E c E v E c Werner, JAP 2011 Brammertz, APL 2009 Close to E c, Al 2 O 3 /InGaAs comparable D it to Al 2 O 3 /Si interface 5

6 Buried-channel vs. surface channel? Classic trade-off: Surface channel: high scalability but low mobility (µ e <2,000 cm 2 /V.s) Buried channel: high mobility but high EOT and t barr µ e 12 nm Al 2 O 3 InP good choice for barrier: wide E g, lattice matched to In 0.53 Ga 0.47 As Urabe, ME

7 HfO 2 vs. Al 2 O 3 in buried-channel MOSFETs D it (x10 12 cm -2 ev -1 ) E V HfO C PDA Al 2 O 3 InP E C E-E i (ev) Galatage - UT Dallas, 2012 I d (A/ m) L g = 150 nm V ds = 50 mv S~85 mv/dec HfO 2 (2 nm) Al 2 O 3 /HfO 2 (0.4/2 nm) V gs (V) HfO 2 (2 nm) directly on InP (1 nm): Low D it close to E c Steep subthreshold swing Low I off (na/μm range) EOT~0.8 nm EOT~1 nm Lin, IEDM

8 HfO 2 in surface-channel MOSFETs EOT~0.5 nm EOT~0.8 nm Lin, IEDM 2013 HfO 2 (2.5 nm) directly on InGaAs: Comparable S as buried-channel device EOT I d Low ALD temperature key D it ~2x10 12 ev -1.cm -2 Suzuki, JAP

Pristine interface for high MOS quality SiO 2 Mo n+ n + cap cap i-inp Channel -Si Semiconductor surface exposed immediately before MOS formation Barrier: InP (1 nm)

9 Pristine interface for high MOS quality SiO 2 Mo n+ n + cap cap i-inp Channel -Si Semiconductor surface exposed immediately before MOS formation Barrier: InP (1 nm) + Al 2 O 3 (0.4 nm) + HfO 2 (2 nm) Lin, IEDM 2012 S = 69 mv/dec at V DS = 50 mv Close to lowest S reported in any III-V MOSFET: 66 mv/dec [Radosavljevic, IEDM 2011] 9

10 Technology issue #2: ohmic contacts Challenge: nanometer-scale ohmic contacts with low R c Tiny (L c < 30 nm) Low contact resistance (R c < 50 Ω.µm) Self-aligned to gate (L side < 10 nm) 10

11 New nano-tlm test structure to characterize short contacts csch 2 csch coth 2 Lu, EDL (submitted) Decouples impact of metal resistance on short contacts 11

Contact-first process for Mo-InGaAs ohmic contacts Fabrication process: Surface cleaning Mo deposition E-beam lithography Mo RIE Mesa isolation Pad

12 Contact-first process for Mo-InGaAs ohmic contacts Fabrication process: Surface cleaning Mo deposition E-beam lithography Mo RIE Mesa isolation Pad metallization Lu, EDL (submitted) Contact anneal Achieved contacts with length down to 19 nm Contact-first process preserves high-quality interface 12

13 Nanometer-scale Mo-InGaAs contacts Mo on n + -In 0.53 Ga 0.47 As: Lu, EDL (submitted) Dormaier JVSTB 2012 Singisetti APL 2008 Baraskar JAP 2013 Crook APL 2007 Lin JAP Ω.μm R c blows up for very small contacts with L c < L t = 113 nm R c ~ 40 Ω.μm for L c ~ 20 nm Average c = m 2 Contacts thermally stable up to 400 o C 13

14 Ni-InGaAs ohmic contact Subramanian, JES 2012 Oxland, EDL 2012 Ni diffused into InGaAs at 250 o C Kim, IEDM 2010 Ni-InGaAs formed Unreacted Ni removed using HCl-based selective etchant R c ~ 50. m demonstrated [Kim VLSI Tech 2013] 14

Technology issue #3: self-aligned MOSFET architectures Challenge: ohmic contacts very closely spaced from gate Design of access region Must maintain high-quality MOS interface and low R c Gate-first

15 Technology issue #3: self-aligned MOSFET architectures Challenge: ohmic contacts very closely spaced from gate Design of access region Must maintain high-quality MOS interface and low R c Gate-first process: silicided S/D Gate-first process: regrown S/D Gate-last process: recessed S/D Hill, IEDM 2010 Kim, VLSI Tech 2013 Egard, IEDM 2011 Zhou, IEDM 2012 Lee, VLSI Tech 2013 Radosavljevic, IEDM 2009 Lin, IEDM

before gate stack formation Process designed to be

16 Gate-last self-aligned InGaAs MOSFETs Ohmic contact first (Mo) Extensive RIE (F-based) Interface exposed immediately before gate stack formation Process designed to be compatible with Si fab RIE damage annealed at 340 o C: Lin, IEDM

8 nm) Wet semiconductor etch L side ~ 30 nm Surface-channel

17 Gate-last self-aligned InGaAs MOSFETs Lin, IEDM 2012 Lin, IEDM 2013 W Mo L g =50 nm L side Buried-channel (EOT~0.8 nm) Wet semiconductor etch L side ~ 30 nm Surface-channel (EOT~0.5 nm) Dry semiconductor etch + digital etch of cap L side ~ 5 nm 17

18 Impact of L side L g = 70 nm L side g m S I on at fixed I off GIDL I on ( A/ m) 500 Lin, IEDM I off =100 na/ m, V dd =0.5 V L g (nm) 18

Technology issue #4: Tri-gate MOSFET Challenge: acceptable I ON and SCE on a small-footprint Planar design does not provide enough electrostatic integrity Need

19 Technology issue #4: Tri-gate MOSFET Challenge: acceptable I ON and SCE on a small-footprint Planar design does not provide enough electrostatic integrity Need tighter channel control through 3D device design Wu, IEDM 2009 Radosavljevic, IEDM 2010 Chin, EDL 2011 Radosavljevic, IEDM 2011 Planar MOSFET Tri-gate MOSFET 19

Direct fin growth by Aspect Ratio Trapping Fin

defects reach surface Inter-diffusion of dopant

etch: self-limiting (2 nm/cycle) No notching in

20 Direct fin growth by Aspect Ratio Trapping Fin formation Fin etch by RIE + digital etch 20 nm Some defects reach surface Inter-diffusion of dopant species BCl 3 /SiCl 4 /Ar RIE chemistry Digital etch: self-limiting (2 nm/cycle) No notching in heterostructures Fiorenza, ECST 2010 Waldron, ECST 2012 Zhao, IEDM

21 Mo contacts to fin Mo Mo-first process Mo used as mask for fin etch Mo sidewall contacts 100 nm Mo Mo on sidewalls With top Mo contact: R c ~ 7 Ω.μm With sidewall contact: R c ~ 12 Ω.μm 21

1 V V GS =0.1 V 0 0.0 0.1 0.2 0.3 0.4 0.5 V GS [V] I D [ A/ m] 1 0.1 W f =35 nm 0.

22 Fin sidewall MOS Double-gate sidewall MOSFET to study sidewall MOS quality Mo SiO 2 25 nm Al 2 O 3 W f =30 nm V GS =0.5 V 10 I D [ A m] 10 5 V GS =0.3 V V GS =-0.1 V V GS =0.1 V V GS [V] I D [ A/ m] W f =35 nm E-3 W f =30 nm 1E-4 W f =25 nm V GS [V] At sidewall: D it ~ 1.4x10 13 ev -1.cm -2 22

Conclusions Remarkable recent progress in InGaAs MOSFETs g m (MOSFET) = g m (HEMT) R on (MOSFET) < R on (HEMT) Very low R c contacts at close to target length Compact, self-aligned devices;

23 Conclusions Remarkable recent progress in InGaAs MOSFETs g m (MOSFET) = g m (HEMT) R on (MOSFET) < R on (HEMT) Very low R c contacts at close to target length Compact, self-aligned devices; link to be engineered to balance performance and SCE Good quality MOS stack close to target EOT Many issues to investigate: Tri-gate technology, integration with p-mosfets on Si, reliability 23

Sub-30 nm InAs Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO 2 Insulator

Sub-30 nm InAs Quantum-Well MOSFETs with Self-Aligned Metal Contacts and Sub-1 nm EOT HfO 2 Insulator Jianqiang Lin, Dimitri A. Antoniadis, and Jesús A. del Alamo Microsystems Technology Laboratories,