Transistors for VLSI, for Wireless: A View Forwards Through Fog

Transcription

1 Plenary, Device Research Conference, June 22, 2015, Ohio State Transistors for VLSI, for Wireless: A View Forwards Through Fog Mark Rodwell, UCSB Low-voltage devices P. Long, E. Wilson, S. Mehrotra, M. Povolotskyi, G. Klimeck: Purdue III-V MOS C.-Y. Huang, S. Lee*, A.C. Gossard, V. Chobpattanna, S. Stemmer, B. Thibeault, W. Mitchell : UCSB InP HBT: J. Rode**, P. Choudhary, A.C. Gossard, B. Thibeault, W. Mitchell: UCSB M. Urteaga, B. Brar: Teledyne Scientific and Imaging Now with: *IBM, **Intel 1

2 Co-authors In(Ga)As MOS THz InP HBT Cheng-Ying Huang Sanghoon Lee Varista Chobpattanna Prof. Susanne Stemmer Johann Rode Prateek Choudhary Steep FET design III-V EPI Process Pengyu Long Evan Wilson Prof. Michael Povolotski Prof. Gerhard Klimeck Prof. Art Gossard Brian Thibeault Bill Mitchell..and at Teledyne (HBT): Miguel Urteaga, Bobby Brar 2

3 What's a Professor to do? Transistors approaching scaling limits Process technology: it's getting hard. extreme resolution, complex process, many steps exhausted students How can we steer the future of VLSI, of wireless? Beyond yet another new semiconductor (be it 3D or 2...) let's explore other options. 3

4 VLSI 4 4

5 I d, Amps/meter What does VLSI need? Small transistors: plentiful, cheap Small transistors short wires small delay CV DD /I low energy CV DD2 /2 Small-area electronics is key Low leakage current thermal: I off > I on *exp(-qv DD /kt) want low V DD yet low I off Want: 0 Large di/dv above threshold Steeper than thermal below threshold V gs mv/decade V gs 5

6 First: Steep-subthreshold-swing transistors I d, Amps/meter mv/decade V gs V gs Characteristics steeper than thermal lower supply voltage 6

7 Tunnel FETs: truncating the thermal distribution Normal T-FET J. Appenzeller et al., IEEE TED, Dec Source bandgap truncates thermal distribution Must cross bandgap: tunneling Fix (?): broken-gap heterojunction 7

8 Tunnel FETs: are prospects good? Useful devices must be small Quantization shifts band edges tunnel barrier Band nonparabolicity increases carrier masses Electrostatics: bands bend in source & channel What actual on-current might we expect? 8

9 Tunneling Probability Transmission Probability (WKB, square barrier) P exp( 2T barrier ), where 2m* E barrier Assume: m* 0.06 m0, E b 0.2 ev Then : P 33% 10% 1% for a 1nm thick barrier for a 2nm thick barrier for a 4nm thick barrier For high I on, tunnel barrier must be *very* thin. ~3-4nm minimum barrier thickness: P+ doping, body & dielectric thicknesses 9

10 Energy, ev Energy(eV) drain current, A/m T-FET on-currents are low, T-FET logic is slow NEMO simulation: GaSb/InAs tunnel finfet: 2nm thick body, 1nm thick e r =12, 12nm L g position, nm Experimental: InGaAs heterojunction HFET; Dewey et al, 2011 IEDM, 2012 VLSI Symp % Transmission mV/dec. 10 ma/mm gate-source bias, volts ~15 Low current slow logic 10

11 Resonant-enhanced tunnel FET Avci & Young, (Intel) 2013 IEDM 2nd barrier: bound state di/dv peaks as state aligns with source improved subthreshold swing. Can we also increase the on-current? 11

12 Electron anti-reflection coatings Tunnel barrier: transmission coefficient < 100% reflection coefficient > 0% want: 100% transmission, zero reflection familiar problem Optical coatings reflection from lens surface quarter-wave coating, appropriate n reflections cancel Microwave impedance-matching reflection from load quarter-wave impedance-match no reflection Smith chart. 12

13 T-FET: single-reflector AR coating Energy(eV) drain current, A/m TFET -0.1 TFET+ one barrier Transmission mV/dec. TFET +one barrier gate-source bias, volts Peak transmission approaches 100% Narrow transmission peak; limits on-current Can we do better? 13

14 Limits to impedance-matching bandwidth Transmission, db Microwave matching: More sections more bandwidth Is there a limit? , 2, 3 sections -5-6 Bode-Fano limits R. M. Fano, J. Franklin Inst., Jan Bound bandwidth for high transmission example: bound for RC parallel load 0 Do electron waves have similar limits? ln 1 2 d -7 RC Frequency, GHz Yes! Schrödinger's equation is isomorphic to E&M plane wave. Khondker, Khan, Anwar, JAP, May 1988 T-FET design microwave impedance-matching problem Fano: limits energy range of high transmission Design T-FETs using Smith chart, optimize using filter theory Working on this: for now design by random search * E / h f, V, I, probability current power,where ( x) ( / jm*)( / x) 14

15 Energy, ev Energy(eV) drain current, A/m T-FET with 3-layer antireflection coating position, nm layer 0-layer Transmission Interim result; still working on design Simulation 60mV/dec. triple layer single layer P-GaSb/N-InAs tunnel FET gate-source bias, volts 15

16 Source superlattice: truncates thermal distribution Proposed 1D/nanowire device: M. Bjoerk et al., U.S. Patent 8,129,763, E. Gnani et al., 2010 ESSDERC Gnani, 2010 ESSDERC Gnani, 2010 ESSDERC: simulation 16

17 Long et al., EDL, Dec Planar (vs. nanowire) superlattice steep FET Planar superlattice FET superlattice by ALE regrowth easier to build than nanowire (?) Performance (simulations): ~100% transmission in miniband. 0.4 ma/mm I on, 0.1mA/mm I off,0.2v Ease of fabrication? Tolerances in SL growth? Effect of scattering? simulation 17

18 What if steep FETs prove not viable? I d, Amps/meter Steep FETs will not be easy mv/dec V gs Instead, increase di/dv above threshold. di/dv: a.k.a. transconductance, g m. Reduced voltage, reduced CV 2 V gs First: III-V MOS as (potential) high-(di/dv) device 18

19 Why III-V MOS? III-V vs. Si: Low m* higher velocity. Fewer states less scattering higher current. Then trade for lower voltage or smaller FETs. Problems: Low m* less charge. Low m* more S/D tunneling. Narrow bandgap more band-band tunneling, impact ionization. 19

20 In(Ga)As: low m* high velocity high current (?) Ballistic on-current: Natori, Lundstrom, Antoniadis (Rodwell) J K 1 K 1 ma 84 mm * 1/ 2 g m mo * 1 ( c / c ) g ( m / m ) 3/ 2 dos, o V equiv gs V 1V th 3/ 2, o 1 c equiv T e g #valleys T ox channel ox 2e semiconductor More current unless dielectric, and body, are extremely thin. normalized drive current K In(Ga)As thin {100} Si 0.4 nm 0.6 nm g=2 g= EET=T e /e +T e /2e EET=1.0 nm ox SiO2 ox channel SiO2 channel m*/m o 20

21 Excellent III-V gate dielectrics Current Density (ma/mm) Gate Leakage (A/cm 2 ) Dot : Reverse Sweep Solid: Forward Sweep L g = 1 mm SS min ~ 61 mv/dec. (at V DS = 0.1 V) SS min ~ 63 mv/dec. (at V DS = 0.5 V) Gate Bias (V) nm ZrO 2 1nm Al 2 O 3 2.5nm InAs V. Chobpattanna, S. Stemmer FET data: S Lee, 2014 VLSI Symp. 61 mv/dec Subthreshold swing at V DS =0.1 V Negligible hysteresis 21

22 I on (ma/mm) Current Density (ma/mm) g m (ms/mm) Record III-V MOS S. Lee et al., VLSI 2014 L g ~25 nm N+ S/D Vertical Spacer L g = 25 nm I on = 500 ma/mm at I off =100 na/mm and V D =0.5V SS~ 72 mv/dec. SS~ 77 mv/dec Gate Bias (V) V DS = 0.5 V I off =100 na/mm S. Lee, VLSI 2014 J. Lin, IEDM 2013 T. Kim, IEDM 2013 Intel, IEDM 2009 J. Gu, IEDM 2012 D. Kim, IEDM 2012 Gate Length (nm) record for III-V = best UBT SOI silicon 22

23 Double-heterojunction MOS: 60 pa/mm leakage L g -30nm L g -30nm C. Y. Huang et al., IEDM 2014 Minimum I off ~ 60 pa/μm at V D =0.5V for L g -30 nm 100:1 smaller I off compared to InGaAs spacer BTBT leakage suppressedisolation leakage dominates 23

24 III-V L g =??? Huang et al., this conference Courtesy of S. Kraemer (UCSB) 24

25 High-current III-V PMOS Silicon PMOS: Wang et al., IEEE TED 2006 (Intel) III-V: S. Mehrotra (Purdue), unpublished nm thickness [110]-oriented PMOS channels low transport mass Very low m* Current approaching NMOS finfets are naturally [110] simulation 25

26 ev from vacuum level Minimum Dielectric Thickness & Gate Leakage Thin dielectrics are leaky Transmissi on Probability P exp( 2T 1 barrier ), where 2m* E barrier High-e r materials have lower barriers E c Si InGaAs HfO TiO E 2 2 v e ~20 e ~40 r r nm minimum EOT constrains on-current electrostatics degrades with scaling fins, nanowires normalized drive current K g=2 0.3 g= nm nm 0.05 EET=T e /e +T e /2e EET=1.0 nm ox SiO2 ox channel SiO2 channel m*/m o 26

27 subthreshold swing, mv/decade Quick check: scaling limits NEMO ballistic simulations finfet: 5 nm physical gate length. Channel: <100> Si, 0.5, 1, or 2nm thick dielectric: e r =12.7, 0.5 or 0.7 nm EOT 80 Dielectric: 0.5 nm EOT 5nm gate length <100> Si finfet Dielectric: 0.7nm EOT thermionic+ tunneling thermionic+ tunneling thermionic only 60 thermionic only body thickness, nm simulation body thickness, nm Given EOT limits, ~1.5-2nm body is acceptable. Source-drain tunneling often dominates leakage. 27

28 Phosphorene Silicon Do 2-D semiconductors help? 3D: Is body thickness a scaling limit? recall the previous slide If oxides won't scale, we must make fins with 2D, can we make fins? later, will need to make nanowires... Ballistic drive currents don't win either high m*, and/or high DOS mobility sufficient for ballistic? ma J K 84 mm where K V ( c / c ) g ( m 1/ m 1/ / m ) 3/ 2 dos, o gs V 1V th g ( m equiv 3/ 2 1/ 2, / m 1/ 2 o ) o MoS 2 normalized drive current K 1 normalized drive current, K 1 normalized drive current, K g=2 isotropic 0.4 nm 0.6 nm EET=1.0 nm m*/m o EET=1.0 nm 0.6 nm 0.4 nm g=6 isotropic normalized effective mass m*/m o EET=1.0 nm 0.6 nm 0.4 nm g=1 transverse mass =2.6*m o 0.05 EET=T e /e +T e /2e ox SiO2 ox channel SiO2 channel normalized longitudinal transport mass m /m L o 28

29 When it gets crowded, build vertically Los Angeles: sprawl Manhattan: dense 2-D integration: wire length # gates 1/2 LA is interconnect-limited 1) Chip stacking (skip) 2) 3D transistor integration 3-D integration: wire length #gates 1/3 29

30 Corrugated surface more surface per die area 30

31 Corrugated surface more current per unit area Cohen-Elias et al., UCSB 2013 DRC J.J. Gu et al., 2012 DRC, Purdue 2012 IEDM 31

32 3D shorter wires less capacitance less CV 2 All three have same drive current, same gate width Tall fin, "4-D": smaller footprint shorter wires 32

33 I d, Amps per meter of FET footprint width Corrugation: same current, less voltage, less CV 2 I d, Amps per meter of FET footprint width I d, Amps per meter of FET footprint width mv/decade :1 corrugation V gs V gs V gs 33

34 Industry is moving to taller fins. 34

35 Fixing source-drain tunneling by increasing mass? Source-drain tunneling leakage: I off exp( 2L g ), where 1 2m*( qv th ) Fix by increasing effective mass? L g constant m* 1/ L 2 g This will decrease the on-current: (also increases transit time) normalized drive current K g=2 0.3 g= nm nm 0.05 EET=T e /e +T e /2e EET=1.0 nm ox SiO2 ox channel SiO2 channel m*/m o?! long gate big shorter gate smaller less current wider more current big again! 35

36 Fixing source-drain tunneling by corrugation Transport distance > gate footprint length Only small capacitance increase 36

37 RF/Wireless 37

38 mm-waves: high-capacity mobile communications wide, useful bandwidths from 60 to ~300 GHz Needs research: RF front end: phased array ICs, high-power transmitters, low-noise receivers IF/baseband: ICs for multi-beam beamforming, for ISI/multipath suppression,... 38

39 mm-wave CMOS won't scale much further Gate dielectric can't be thinned on-current, g m can't increase 0.35 Shorter gates give no less capacitance dominated by ends; ~1fF/mm total normalized drive current K nm 0.6 nm 0.3 nm 0.05 EET=T e /e +T e /2e EET=1.0 nm ox SiO2 ox channel SiO2 channel m*/m o Maximum g m, minimum C upper limit on f t. about GHz. Tungsten via resistances reduce the gain Inac et al, CSICS 2011 g=1 Present finfets have yet larger end capacitances 39

40 III-V high-power transmitters, low-noise receivers Cell phones & WiFi: GaAs PAs, LNAs mm-wave links need high transmit power, low receiver noise 0.47 H Park, UCSB, IMS T Reed, UCSB, CSICS 2013 M Seo, TSC, IMS

41 Making faster bipolar transistors to double the bandwidth: change emitter & collector junction widths decrease 4:1 current density (ma/mm 2 ) increase 4:1 current density (ma/mm) constant collector depletion thickness decrease 2:1 base thickness decrease 1.4:1 emitter & base contact resistivities decrease 4:1 Teledyne: M. Urteaga et al: 2011 DRC Narrow junctions. Thin layers High current density Ultra low resistivity contacts 41

42 THz HBTs: The key challenges Obtaining good base contacts in full HBT process flow (vs. in TLM structure) RC parasitics along finger length metal resistance, excess junction areas 10-5 P-InGaAs 10-6 Contact Resistivity, cm THz target B =0.8 ev 0.6 ev 0.4 ev 0.2 ev step-barrier Landauer Hole Concentration, cm -3 Baraskar et al, Journal of Applied Physics,

43 THz InP HBTs blanket Pt/Ru base contacts: resist-free, cleaner surface lower resistivity J. Rode, in review 43

44 THz HEMTs: one more scaling generation? First Demonstration of Amplification at 1 THz Using 25- nm InP High Electron Mobility Transistor Process Xiaobing Mei, et al, IEEE EDL, April 2015 doi: /LED

45 nm & THz electronics 45

46 Electron devices: What's next? Problems: oxide, S/D tunneling lithography interconnect energy Why transistors are best: our best tools are: ~ l/n deep UV absorption..electrostatic control of charge & static dissipation...and communicating by E&M waves Opportunities: low voltages high currents nm via 3D RF THz 46

47 (backup slides follow) 47