100+ GHz Transistor Electronics: Present and Projected Capabilities

Transcription

1 21 IEEE International Topical Meeting on Microwave Photonics, October 5-6, 21, Montreal 1+ GHz Transistor Electronics: Present and Projected Capabilities Mark Rodwell University of California, Santa Barbara , fax

2 THz Transistors

3 Why Build THz Transistors? 5 GHz digital logic fiber optics THz amplifiers THz radios imaging, sensing, communications precision analog design at microwave frequencies high-performance receivers Higher-Resolution Microwave ADCs, DACs, DDSs

4 gains, db Transistor figures of Merit / Cutoff Frequencies H 21 =short-circuit current gain MAG = maximum available power gain: impedance-matched f max power-gain cutoff frequency f current-gain cutoff frequency U= unilateral power gain: feedback nulled, impedance-matched

5 What Determines Digital Gate Delay? T gate ( kt f R R ( V ex bb / qi L C (.5C (.5C / )( C )(.5C cbx je I C je.5c C cbi je 6C C cbi cbx cbx.5 I C f C 6C cbi.5 I f C / V cbi.5 I / V L ). C L f ) wire C ) / V L ) CV/I terms dominate analog ICs have somewhat similar bandwidth considerations...

6 How to Make THz Transistors

7 High-Speed Transistor Design Depletion Layers C A T Fringing Capacitances T 2v C finging / L ~ C finging / L ~ 4v ( V ) max sat appl 2 I A T Thermal Resistance Bulk and Contact Resistances R th 1 K th ln L L W 1 K th L R / contact A contact terms dominate

8 Frequency Limits and Scaling Laws of (most) Electron Devices thickness C R R I top T bottom area / contact area power length thickness contact max, space-charge-limit / area 4 log sheet area / length width width length thickness PIN photodiode To double bandwidth, reduce thicknesses 2:1 Improve contacts 4:1 reduce width 4:1, keep constant length increase current density 4:1 2 R bottom R top

9 Changes required to double transistor bandwidth emitter length L E W e HBT parameter change emitter & collector junction widths decrease 4:1 current density (ma/mm 2 ) increase 4:1 current density (ma/mm) constant collector depletion thickness decrease 2:1 base thickness decrease 1.4:1 emitter & base contact resistivities decrease 4:1 nearly constant junction temperature linewidths vary as (1 / bandwidth) 2 gate L G widthw G FET parameter change gate length decrease 2:1 current density (ma/mm), g m (ms/mm) increase 2:1 channel 2DEG electron density increase 2:1 gate-channel capacitance density increase 2:1 dielectric equivalent thickness decrease 2:1 channel thickness decrease 2:1 channel density of states increase 2:1 source & drain contact resistivities decrease 4:1 constant voltage, constant velocity scaling fringing capacitance does not scale linewidths scale as (1 / bandwidth )

10 Electron Plasma Resonance: Not a Dominant Limit L R kinetic bulk T A q T A q * nm 1 * nm m C displacement A T dielectric f dielectric relaxation C 1 2 1/ 2 R displacement frequency bulk scattering frequency f scattering 1 R 2 L 1 2 m bulk kinetic plasma frequency f plasma L kinetic 1/ 2 C displaceme nt n - InGaAs / cm p - InGaAs / cm THz 7 THz 74 THz 8 THz 12 THz 31THz

11 junction temperature rise, Kelvin Thermal Resistance Scaling : Transistor, Substrate, Package cylindrical heat flow near junction spherical flow for r L e planar flow for r D HBT / 2 P L e P 1 1 P Tsub D / 2 T substrate ln 2 K InPLE We K InP LE D KInP D increases logarithmi cally insignific ant variation increases quadratically if T sub is constant T package K P Cu chip W chip 14 T 4 mm (15 GHz / f ) sub clock HBT CMLIC total 1 8 substrate: cylindrical+spherical regions 6 4 package 2 substrate: planar region master-slave D-Flip-Flop clock frequency, GHz Wiring lenghts scale as 1/bandwidth. Power density, scales as (bandwidth) 2.

12 junction temperature rise, Kelvin Thermal Resistance Scaling : Transistor, Substrate, Package cylindrical heat flow near junction spherical flow for r L e planar flow for r D HBT / 2 P L e P 1 1 P Tsub D / 2 T substrate ln 2 K InPLE We K InP LE D KInP D increases logarithmi cally insignific ant variation increases quadratically if T sub is constant T package K P Cu chip W chip 14 T sub 4 mm (15 GHz / f ) clock 12 total 2 - HBT CMLIC 1 Probable best solution: scale as Thermal Vias ~5 nm below InP subcollector 1/bandwidth. Power density, 8 substrate: cylindrical+spherical regions 6 4 package 2 substrate: planar region over full active IC area. master-slave D-Flip-Flop clock frequency, GHz Wiring lenghts scales as (bandwidth) 2.

13 Bipolar Transistors

14 db db db 256 nm InP HBT 34 GHz dynamic frequency divider M. Seo, UCSB/TSC 34 GHz VCO M. Seo, UCSB/TSC IMS GHz amplifier J. Hacker, TSC IMS 21 VEE Vtune Vout VBB 15 nm thick collector nm thick collector Hz Z. Griffith H 21 f = 424 GHz U 1 1 f max = 56 GHz f = 56 GHz Hz U f max = 78 GHz 1 11 H 21 E. Lind 1 12 ma/mm 2 ma/mm V ce V ce 24 GHz static frequency divider Z. Griffith, TSC CSIC 21: to be presented H 21 U Z. Griffith 2 1 f = 218 GHz 1 max f = 66 GHz t much better results in press... V Hz ce ma/mm 2 3

15 InP Bipolar Transistor Scaling Roadmap emitter nm width mm 2 access base nm contact width, mm 2 contact collector nm thick, ma/mm 2 current density V, breakdown f GHz f max GHz power amplifiers GHz digital 2:1 divider GHz T b W e W bc T c

16 Fabrication Process for 128 nm & 64 nm InP HBTs

17 Chart 17 Gain (db) Initial Results: Refractory-Contact HBT Process Gain (db) 11 nm emitter width 27 nm emitter width 3 U 25 2 H 21 f = 7 GHz max 15 1 A =.11 mm x 3.5 mm je 5 f = 37 GHz t Freq (Hz) U H 21 A je =.27mm x 3.5mm f t = 43 GHz f max = 8 GHz freq (Hz) Need to add E-beam defined base, best base contact technology

18 f max (GHz) InP DHBTs: August GHz 5 GHz 6 GHz 2 nm 7 GHz 8 GHz 9 GHz f max f Teledyne DHBT UIUC DHBT NTT DBHT popular metrics : f ( f (1 f f or f f f max max 1 max alone ) / 2 f max ) nm 11 nm 25 nm 6nm 35 nm Updated Aug f t (GHz) ETHZ DHBT UIUC SHBT UCSB DHBT NGST DHBT HRL DHBT IBM SiGe Vitesse DHBT much better power amplifiers : PAE, associated gain, mw/ mm low noise amplifiers : F digital : f ( C ( R ( R ( τ min clock b cb ex bb, associated gain, I, hence V / I I c c τ / V ), / V ), c ) c ), metrics :

19 67 GHz Transceiver Simulations in 128 nm InP HBT nf(2) db(s(2,1)) nf(2) db(s(2,1)) Vout, Vout_bar PLL single-sideband phase noise spectral density, dbc (1 Hz) Noise Figure, Conversion Gain (db) nf(2) db(s(2,1)) Vout, Vout_bar transmitter exciter 67 GHz (128 nm HBT) receiver LNA: 9.5 db Fmin at 67 GHz SP.freq, GHz freq, GHz VCO: -5 dbc (1 1 Hz offset at 62 GHz (phase 1) PA: 9.1 dbm Pout at 67 GHz nm 64nm 128nm SP.freq, GHz freq, GHz (a) (b) (a) (c) Total PLL phase noise free-running VCO SP.freq, THz freq, THz -1 closed-loop VCO noise multiplied reference noise offset from carrier, Hz 3-layer thin-film THz interconnects thick-substrate--> high-q TMIC thin -> high-density digital Dynamic divider: novel design, simulates to 95 GHz GHz Input GHz Input time, seconds time, seconds Mixer: 1.4 db noise figure 11.9 db gain LO Power

20 THz Field-Effect Transistors (THz HEMTs)

21 FET Scaling Laws L G Changes required to double device / circuit bandwidth. laws in constant-voltage limit: FET parameter change gate length decrease 2:1 current density (ma/mm), g m (ms/mm) increase 2:1 channel 2DEG electron density increase 2:1 electron mass in transport direction constant gate-channel capacitance density increase 2:1 dielectric equivalent thickness decrease 2:1 channel thickness decrease 2:1 channel density of states increase 2:1 source & drain contact resistivities decrease 4:1 gate widthw G

22 HEMT/MOSFET Scaling: Four Major Challenges contact regions: need reduced access resistivity gate dielectric: need thinner barriers tunneling leakage channel: need higher charge density yet keep high carrier velocity channel: need thinner layers

23 THz FET Scaling Roadmap? Gate length nm Gate barrier EOT nm well thickness nm S/D resistance mm effective mass *m # band minima f GHz f max GHz f divider source-coupled logic GHz I d /W 2 mv overdrive ma/mm high-k gate dielectrics source / drain regrowth G-L transport

24 III-V MOSFETs with Source/Drain Regrowth 27 nm InGaAs MOSFET

25 Regarding Mixed-Signal ICs & Waveform Generation

26 Clock Timing Jitter in ADCs and DACs Timing jitter is quantitatively specified by the single-sideband phase noise spectral density L(f). IC oscillator phase noise varies as ~1/f 2 or ~1/f 3 near carrier Impact on ADCs and DACs: imposition of 1/f n sidebands on signal of relative amplitude L(f)...not creation of a broadband noise floor. Dynamic range of electronic DACs & ADCs is limited by factors other than the phase noise of the sampling clock

27 Why ADC Resolution Decreases With Sample Rate Dynamic Range Determined by Circuit Settling Time vs. Clock Period dynamic hysteresis metastability # bits 1 f sample latch IC time constants Resolution decreases at high sample rates

28 Fast IC Waveform Generation: General Prospects Waveform generator fast digital memory & DAC Parallel digital memory and 2 Gb/s MUX is feasible cost limits: power & system complexity vs. # bits, GS/s Performance limit: speed vs. resolution of DAC faster technologies increased sample rates Feasible ADC resolution: 12 SNR 4 GS/s feasible using 5 nm (4GHz) InP HBT. Feasible sample rate will scale with technology speed..

29 THz Transistors & Mixed-Signal ICs

30 Few-THz Transistors Few-THz InP Bipolar Transistors: can it be done? Scaling limits: contact resistivities, device and IC thermal resistances. 62 nm (1 THz f, 1.5 THz f max ) scaling generation is feasible. 7 GHz amplifiers, 45 GHz digital logic Is the 32 nm (1 THz amplifiers) generation feasible? Few-THz InP Field-Effect Transistors: can it be done? challenges are gate barrier, vertical scaling, source/drain access resistance, channel density of states. 2DEG carrier concentrations must increase. S/D regrowth offers a path to lower access resistance. Solutions needed for gate barrier: possibly high-k (MOSFET) Implications: 1 THz radio ICs, ~2-4 GHz digital ICs, 2 GHz ADCs/DACs