Ultra High-Speed InGaAs Nano-HEMTs
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1 Ultra High-Speed InGaAs Nano-HEMTs Kwang-Seok Seo School of Electrical Eng. and Computer Sci. Seoul National Univ., Korea Contents Introduction to InGaAsNano-HEMTs Nano Patterning Process beyond Lithography Limit - Side-wall Gate Process - 50nm In 0.65 GaAs HEMT s New Triple Shaped Gate Process - 30nm Sidewall Process & Triple Gate Using BCB Planarization - 30nm In 0.7 GaAs HEMT s with high cut-off frequency (f T ) Application of InGaAs Nano-HEMT Devices - 110GHz Wideband Distributed Amplifier MMIC - RTD & HEMT Digital IC : 20Gbps MOBILE Summary
2 Millimeter-Wave/Tera-Hz Technology Broad Bandwidth High Speed Data Communication Small Size Antenna Mobile Communication/Automobile Radar High Resolution Imaging Biomedical Imaging ( > 100GHz) Auto. Radar Millimeter wave Demands for High Frequency/High Performance Devices & Circuits Nano-technology enhances the speed of devices & circuits. (due to the reduction of carrier transit time) State-of-the-art InGaAs Nano-HEMT s n + InGaAs InP InAlAs In 0.7 GaAs CRL-Fujitsu Group s Work (02,EDL) Gate Length = 25nm In 0.7 GaAs Channel (with v peak ~3.4x10 7 cm/s) f T =562GHz (World Record) * Fabricated by the state-of-the-art E-beam lithography system
3 How to to improve ff T of of Nano-HEMT s? L g Reduction : L g < 30nm T-Gate Metal R g Strained Channel (In x GaAs) - Indium Content > 0.7 for Higher v average C par Structure for Small Parasitics L g SiO 2 / Recess InGaAs/InAlAs Epi-Wafer < Cross-section of Nano-HEMT s > - Reduction of L g,2nd (<100nm) - Increase of Height (>150nm) f T Enhancement Two-Step Recess Etching - Damage-Free Condition Structural Stability - Wide T-Gate : Small R g Nano Patterning beyond Lithography Limit PR Trimming By Plasma Asing Side-wall Process Photo-resist Flow Process RIE Lag Effect
4 Low-Damage & Reproducible Side-wall Process Oxide Two-step Etch-back - CF 4 /O 2 Mixture : Etching SiO 2 < 1 st Line Definition & Re -depo. > Oxide < Oxide Etch-back by CF 4 Plasma > Oxide - SF 6 /Ar Mixture : Etching the residual 1) Lower Damage than that of other gas 2) Etch Selectivity of over SiO 2 - Typical Selectivity = ~ 20 L g,final : Insensitive to over-etch cond. Low-Damaged & Reproducible L g,final L g,final = ~ L g,initial / 2 < Etch-back by SF 6 Plasma > Sidewall Process Results :: 50nm Line PMMA SiO 2 L g = 100nm (a) 1 st Gate Definition (c) Etch-Back : On Etching Sidewall Void L g = 50nm (b) SiO 2 Re-deposition (d) Final Sidewall Gate
5 50nm Double Decked T- T-Gate Fabrication T-Gate Metal Photo -Resist PMMA copolymer T-gate defined by EBMF 10.5 C par_1 C par_2 C par_2 C par_1 PMMA(200nm) (100nm) Gate foot defined by Side-wall Process Reduction of C parasitics for Higher f T 200nm 50nm Epitaxial Structures for Nano-HEMT Fabrication δ-doping Spacer < Epitaxial Structure > 19 n+ InGaAs Cap. 1X10 20nm i InP Etch-stopper 4nm i In i In i In i In AlAs Barrier 8nm GaAs Channel 10nm GaAs Channel 10nm 0.52 AlAs Buffer 500nm S.I. InP Substrate < Cross-Section of Nano-HEMT > Passivation Layer Selective Wet Etch In 0.53 GaAs InPEtch-stopper In 0.52 AlAs Barrier In 0.52 AlAs Spacer In 0.65 GaAs Strained Channel In 0.53 GaAs Pre-Channel Schottky On InAlAs Ar-RIE with Low Damage Si Delta-Doping n s =3x10 12 /cm 2, m n,hall =10,300cm 2 /V-s
6 50nm InGaAs Nano-HEMT :: DC Characteristics < L g = 50nm & 65% Strained InGaAs Channel > V th = -0.6V & G m,max = V ds = 1.0V 50nm InGaAs Nano-HEMT: Microwave Characteristics - Bias Point : Maximum Transconductance Condition - f T =305GHz f T = 305 GHz & f max = 302GHz
7 InGaAs Nano-HEMT s :: Metal Filling Issue High Performance Nano-HEMTs L g, T-Gate Aspect Ratio (For Small C parasitics ) metal filling of fine line with high A-R needed. < Gate Filling By E-Beam Evaporation> Metal SiO 2 Epi - Structure < Gate Filling By W-Sputtering> Only 60nm Filling W=150nm L g =40nm H=200nm W Filling Aspect Ratio (H/L g ) = 5 Not Filled After 50nm Evaporation Good Gate Metal Filling W : Good Thermal Reliability T-Gate Process for 30nm InGaAs HEMT s High Temp. Sputter : Problem in Lift-off Metal Etch Process High Temp. Sputter PMMA Lift-off & W-Etch Tusten (W) Epi-wafer W Epi-wafer PMMA Good Filling BCB Planarization BCB W Epi-wafer BCB Etch-Back & Head Litho. BCB W Epi-wafer < New Triple Gate Process Using High Temp. Sputter & BCB Planarization >
8 30nm In In GaAs HEMT s :: DC I-V < L side-etch = 50nm & No InP Etch > < L side-etch = 50nm & InP Etch> Schottky on InP/InAlAs (4/10nm) Schottky on InAlAs (10nm ) => V th = -0.85V & G m,max = 1.75S/mm => V th = -0.3V & G m,max = 1.69S/mm => High Short channel effect G m /G ds = G m,max Bias Point => Low Short channel effect G m /G ds = G m,max Bias Point RF Characteristics of of 30nm In In GaAs HEMT s < f T versus Gate Bias > < Best f T Charateristics > f T = 421GHz at V gs / V ds = / 1.05V
9 Performances of of SNU InP Nano-HEMT s < f T versus L g > f T L G 1 = 2 π v L reduction sat G, eff decrease of τ transit increase of f T (2003) ( 2002) (2001) SNU InGaAs Nano-HEMT f T = 250GHz for L g =60nm f T = 305GHz for L g =50nm f T = 371GHz for L g =40nm f T = 421GHz for L g =30nm Over 110GHz Broadband Distributed Amplifier Output+V D Unit cell - Chip size:1.5x0.7mm 2 - Output+V D Input+V G1 V G2 < Schematic of distributed amplifier > Input+V G1 V G2 < Photograph of distributed amplifier > < Measured S-parameter > Broadband distributed amplifier with 60nm InGaAs Nano-HEMT The average gain at 1~110GHz is about 6.6 db. S 11 < -11 db, S 22 < -4 db
10 RTD & HEMT Digital IC IC 20Gbps MOBILE RTD HEMT BCB Current Density(kA/cm 2 ) PVCR ~ 9 J peak > 5.5x10 4 A/cm Voltage [V] I DS [ma/mm] G m ~ 1.1 S / mm f T = 180GHz V DS [V] Chip size : 0.75X0.68mm 2 50 psec 250 mv P-P < RTD I-V Curve > < HEMT I-V Curve : L g =100nm > 20Gbps PRBS Output Signal Summary Nano Patterning Method beyond Lithography Limit - Sidewall Process / Resist Flowing / Sloped Etch By RIE-Lag 30nm In 0.7 GaAs Nano-HEMT - Sidewall Process + Triple Gate Process Using BCB Planarization - G m,max = 1.75S/mm & f T = 421GHz Application of Developed InGaAs Nano-HEMT Device - 110GHz Wideband Distributed Amplifier (DA) MMIC : B-W > 110GHz - MOBILE IC based on RTD & HEMT Integration > 20Gbps In future, the high speed characteristics of InGaAs nano-hemt are to be enhanced with nano-technology [reduction of gate length], and ultra-high-speed ICs are to be implemented with nano-hemts.
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