Progress Energy Distinguished University Professor Jay Baliga. April 11, Acknowledgements

Transcription

1 Progress Energy Distinguished University Professor Jay Baliga April 11, 2019 Acknowledgements 1

2 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 2

3 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 3

4 PRESiCE: PRocess Engineered for manufacturing SiC Electronic-Devices SiC Power Electronic-Devices B.J. Baliga, et al, "PRESiCE TM : Process Engineered for manufacturing SiC Electronic-Devices", Int. Conf. on Silicon Carbide and Related Materials, Paper MO.CP.10, September 18,

5 PRESiCE: PRocess Engineered for manufacturing SiC Electronic-Devices Qualification Procedure: (1) Define Process Flow (NCSU) for Manufacturing SiC Power MOSFETs, JBSFETs, and JBS Rectifiers at X-Fab. (2) Design a Mask Set (NCSU) for Manufacturing SiC Power MOSFETs, JBSFETs, and JBS Rectifiers at X-Fab for Qualifying the process. (3) Fabricated Three Process Lots at X-Fab. (4) Obtained Statistical Data (NCSU) on device parameters to confirm tight distribution of parameters from within each wafer, from wafer-towafer within each process lot, and from lot-to-lot. Data Acquisition Equipment: (1) New Semi-Automated Signatone Wafer Prober. - 6 inch wafer capability - 3 kv chuck isolation - High Temp (300 oc) (2) New Keysight Test Equipment. - Maximum Voltage = 3 kv - Maximum Current = 20 A 5

6 1.2 kv JBS Rectifier Process Qualification Process Qualification using Three Lots at X-Fab Device #2: JBS Rectifier with Nickel Schottky Contact Active Area = cm2 W. Sung, K. Han and B.J. Baliga, "Design and Manufacturing of 1200 V SiC JBS Diodes with Low On-State Voltage Drop and Reverse Blocking Leakage Current", Int. Conf. on Silicon Carbide and Related Materials, Paper WE.DP.9, September 20, inch SiC wafer fabricated at X-Fab

7 JBS Rectifier with Nickel Schottky Contact (Within Lot Variation) On-state Voltage Drop If = 5A Lot-3-W3-#2 Lot-3-W6-#2 Std. Dev. : 0.05 Std. Dev. : 0.06 Average = 2.00 V Average = 2.05 V 7

8 JBS Rectifier with Nickel Schottky Contact (Within Lot Variation) Leakage Current (I L ) Vd=1000 V, RT Lot-3-W3-#2 Lot-3-W6-#2 Yield : 98.7% Yield : 95.3% Yield based on allowable maximum leakage current of 100 µa 8

9 JBS Rectifier with Nickel Schottky Contact (Lot-to-Lot Variation) Lot-3-W3-#2 On-state Voltage Drop if = 5A, RT Lot-4-W3-#2 Lot-5-W3-#2 Std. Dev. : 0.05 Std. Dev. : 0.03 Std. Dev. : 0.07 Average = 2.00 V Average = 1.94 V Average = 2.06 V

10 JBS Rectifier with Nickel Schottky Contact (Lot-to-Lot Variation) Leakage Current (I L ) Vd=1000 V, RT Lot-5-W3-#2 Lot-3-W3-#2 Lot-4-W3-#2 Yield : 98.7% Yield : 94.7% Yield : 96.7% Yield based on allowable maximum leakage current of 100 µa 10 10

11 Accumulation Channel MOSFET (ACCUFET) Process Qualification using Three Process Lots at X-Fab Device #5: Accumulation Channel MOSFET (ACCUFET) with JFET Implant Active Area = cm2 Technical Note: W. Sung, K. Han and B.J. Baliga, "A Comparative Study of Channel Designs for SiC MOSFETs: Accumulation-Mode Channel vs Inversion-Mode Channel", IEEE Int. Symp. On Power Semiconductor Devices and ICs, Paper SiC-P9, pp , June 2017, Sapporo, Japan. The Rds,on values in the Wafer Maps and Statistical Data plots include 35 mω of parasitic probe (~ 1 mω-cm2) and substrate (~ 1 mω-cm2) resistance. The Cgd values in Wafer Maps and Statistical data include 0.5 pf of parasitic probe capacitance.

12 Accumulation Channel MOSFET (ACCUFET) (Within Lot Variation) On-Resistance (R on ) Id=1A, Vg=25V, RT mω-cm2 Lot-4-W1-#5 Lot-4-W2-#5 Damaged during the BV test w/o Flourinert Std. Dev. : 5.57 Typical value is the Average of All Devices from All Three Lots Std. Dev. : 3.29 Average = 139 mω Average = 137 mω Typical: 144 mω (Allowable Max : 187 mω (30 % more)) All devices meet specifications 12

13 Accumulation Channel MOSFET (ACCUFET) (Within Lot Variation) Threshold Voltage (V th ) Id = 1 ma, Vd = 0.1 V, RT Lot-4-W1-#5 Lot-4-W2-#5 Std. Dev. : 0.14 Typical value is the Average of All Devices from All Three Lots Std. Dev. :0.16 Average = 2.03 V Average = 2.48 V Typical : 2.33 V (Allowable Max : 3.50 V (50 % more)) All devices meet specifications 13

14 Accumulation Channel MOSFET (ACCUFET) (Within Lot Variation) Lot-5-W1-#5 Cgd Vd=1000 V, RT Lot-5-W2-#5 Std. Dev. :0.489 Std. Dev. :0.543 Average = 9.51 pf Average = 9.86 pf

15 Accumulation Channel MOSFET (ACCUFET) (Within Lot Variation) Leakage Current (I L ) Vd=1000 V, RT Lot-4-W1-#5 Lot-4-W2-#5 Yield : 95.3% Yield : 92.7% Yield based on allowable maximum leakage current of 100 µa 15

16 Accumulation Channel MOSFET (ACCUFET) (Lot-to-Lot Variation) Lot-3-W1-#5 On-Resistance (R on ) Id=1A, Vg=25V, RT Lot-4-W1-#5 Lot-5-W1-#5 Damaged during the BV test w/o Flourinert Std. Dev. : 2.75 Std. Dev. : 5.57 Std. Dev. : 3.60 Average = 149 mω Average = 139 mω Average = 150 mω Typical : 144 mω (Allowable Max : 187 mω (30 % more)) All devices meet specifications 16

17 Accumulation Channel MOSFET (ACCUFET) (Lot-to-Lot Variation) Threshold Voltage (V th ) Id = 1 ma, Vd = 0.1 V, RT Lot-3-W1-#5 Lot-4-W1-#5 Lot-5-W1-#5 Std. Dev. : 0.13 Std. Dev. : Std. Dev. : Average = 2.33 V Average = 2.03 V Average = 2.36 V Typical : 2.33 V (Allowable Max : 3.50 V (50 % more)) All devices meet specifications 17

18 Accumulation Channel MOSFET (ACCUFET) (Lot-to-Lot Variation) Lot-3-W1-#5 Cgd Vd=1000 V, RT Lot-4-W1-#5 Lot-5-W1-#5 Damaged during the BV test w/o Flourinert Std. Dev. :0.21 Std. Dev. :0.25 Std. Dev. :0.49 Average = pf Average = 9.64 pf Average = 9.51 pf 18

19 Accumulation Channel MOSFET (ACCUFET) (Lot-to-Lot Variation) Leakage Current (I L ) Vd=1000 V, RT Lot-3-W1-#5 Lot-4-W1-#5 Lot-5-W1-#5 Yield : 93.3 % Yield : 95.3% Yield : 96% Yield based on allowable maximum leakage current of 100 µa 19

20 Inversion Channel MOSFET (INVFET) Process Qualification using Three Process at X-Fab Device #5: Inversion Channel MOSFET (INVFET) with JFET Implant Active Area = cm2 Similar Results like Accumulation Channel devices PRESiCE Technology is available for licensing from NCSU for manufacturing products at X-Fab 20

21 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor

22 JBSFET: MOSFET with Integrated JBS Diode Inter layer dielectric P+ohmic N+ohmic Poly-Gate MOSFET Cell pitch 11um Simulated R on,sp =6.8 mω cm 2 (assuming µ ch =13 cm 2 /V s) P+source N+source Channel JFET region P-body Drift layer N d = cm -3 W d =10um Inter layer dielectric Schottky P+ohmic N+ohmic Poly-Gate JBSFET Cell pitch 16um R on,sp =10 mω cm 2 (assuming µ ch =13 cm 2 /V s) P+source N+source Channel JFET region P-body Drift layer N d = cm -3 W d =10um W. Sung and B.J. Baliga, "On Developing One-Chip Integration of 1.2 kv SiC MOSFET and JBS Diode (JBSFET)", IEEE Transactions on Industrial Electronics, Vol. 64, pp ,

23 JBSFET Area Savings Analysis Layout comparison for 1.2 kv, 5.7 A Devices Approaches Active area (cm2) Edge termination And periphery Total area (cm2) Previous approach Pure MOS FET + Pure JBS (MOSFET) (JBS) (MOSFET) (JBS) = PA approach 1 JBSEFET1 JBSFET (5.72A MOSFET*) PA approach 2 JBSFET2 JBSFET PA approach 3 JBSFET3 Pure MOS FET Pure JBS Assumptions: Edge termination design : 10 floating field rings 3um wide, total spacing is about 20um, which gives about 50um total width for edge termination Periphery : Edge termination to C/S implant 20um, dicing lane 70um per side, C/S to dicing 30um-> total 120um *Comparison with a 5.72A pure MOSFET : active periphery = cm2 23

24 JBSFET Area Savings Analysis Conclusion: Area Savings of about 40 % can be achieved with the JBSFET Approach Other Benefits: Cuts package count in half. Reduces switching loss by 40% at elevated temperatures. 24

25 Measured Data - JBSFET I-V JBSFET Id-Vd, Active area 4.5mm 2 Drain Current (A) st Quadrant JBSFET 3 rd Quadrant Drain Voltage (V) Vg=25V Vg=20V Vg=15V Vg=10V Vg=5V Vg=0V MOSFET Vg=-5V MOSFET Vg=0V Drain Voltage (V) JBSFET Vg=-5V, 0V Drain Current (A) Specific on resistance: 20 mohm-cm Vg = 25 V JBSFET V(on) at 5A: 2 V MOSFET V(on) at 5A: 4.5 V 25

26 Accumulation Channel JBSFET Process Qualification using Three Process Lots at X-Fab Device #7: Accumulation Channel JBSFET with JFET Implant Active Area = cm2 Inter layer dielectric Schottky P+ohmic N+ohmic Poly-Gate P+source N+source Channel JFET region P-body W. Sung and B.J. Baliga, "Monolithically Integrated 4H-SiC MOSFET and JBS Diode (JBSFET) using a Single Ohmic/Schottky Process Scheme", IEEE Electron Device Letters, Vol. 37, pp , Technical Note: The Rds,on values in the Wafer Maps and Statistical Data plots include 35 mω of parasitic probe (~ 1 mω-cm2) and substrate (~ 1 mω-cm2) resistance. The Cgd values in Wafer Maps and Statistical data include 0.5 pf of parasitic probe capacitance. 26

27 Accumulation Channel JBSFET (Lot-to-Lot Variation) On-Resistance (R on ) Id=1A, Vg=25V, RT 11 mω-cm2 Lot-3-W3-#7 Lot-4-W3-#7 Lot-5-W3-#7 Std. Dev. : Std. Dev. : 7.05 Std. Dev. : 16.6 Average = 250 mω Average = 232 mω Average = 268 mω Typical : 250 mω (Allowable Max : 325 mω (30 % more)) All devices meet specifications 27

28 Accumulation Channel JBSFET (Lot-to-Lot Variation) Threshold Voltage (V th ) Id = 1 ma, Vd = 0.1 V, RT Lot-3-W3-#7 Lot-4-W3-#7 Lot-5-W3-#7 Std. Dev. : 0.10 Std. Dev. : 0.11 Std. Dev. : 0.11 Average = 2.43 V Average = 2.31 V Average = 2.50 V Typical : 2.41 V (Allowable Max : 3.62 V (50 % more)) All devices meet specifications 28

29 Accumulation Channel JBSFET (Lot-to-Lot Variation) 3 rd Quadrant (V f ) [V]@ If = 5A, RT Lot-3-W3-#7 Lot-4-W3-#7 Lot-5-W3-#7 Std. Dev. : Std. Dev. : Std. Dev. : Average = 2.25 V Average = 2.21 V Average = 2.33 V 29

30 Accumulation Channel JBSFET (Lot-to-Lot Variation) Leakage Current (I L ) Vd=1000 V, RT Lot-3-W3-#7 Lot-4-W3-#7 Lot-5-W3-#7 Yield : 95.3% Yield : 93.3% Yield : 94.7% Yield based on allowable maximum leakage current of 100 µa 30 30

31 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 31

32 Split-Gate (SG) SiC Power MOSFET Conventional Split-Gate The Split-Gate SiC Power MOSFET can be fabricated with the same process as used for the Conventional MOSFET. Gate Design is different during device layout. 32

33 Split-Gate (SG) SiC Power MOSFET Conventional MOSFET Optimum X is 0.3 µm based on alignment tolerances 33

34 Split-Gate (SG) SiC Power MOSFET: Experimental Results Cgd 34

35 Split-Gate (SG) SiC Power MOSFET: Experimental Results TABLE I SUMMARY OF EXPERIMENTAL RESULTS FOR CONVENTIONAL MOSFET AND SG-MOSFET MOSFET SG-MOSFET Breakdown voltage [V] Threshold voltage [V] R on,sp [mω-cm2] C gd,sp [pf/cm 2 ] (@V d =0V) C gd,sp [pf/cm 2 ] (@V d =1kV) Q gd,sp [nc/cm 2 ] FOM <R C (@V d =0V)> [mω-pf] FOM <R C (@V d =1kV)> [mω-pf] x Improvement FOM <R Q> [mω-nc] x Improvement K. Han, B.J. Baliga, and W. Sung, "Split-Gate 1.2 kv 4H-SiC MOSFET: Analysis and Experimental Validation", IEEE Electron Device Letters, Vol. 38, pp , October

36 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 36

37 Buffered-Gate (BG) SiC Power MOSFET Conventional Split-Gate Buffered-Gate The Buffered-Gate SiC Power MOSFET can be fabricated with one additional (N+ JFET) Step compared with the Conventional MOSFET. Gate Design is different during device layout. 37

38 Buffered-Gate (BG) SiC Power MOSFET Ron,sp (mohm-cm 2 ) Optimum X 1 = 0.4 µm, X 2 = 0.1 µm Inv. BG- MOSFET Accu. BG- MOSFET Oxide Field (MV/cm) 0 2E+17 4E+17 6E+17 8E+17 1E+18 Doping concentration (cm -3 ) Optimization of N+ JFET Doping Concentration 3E17 cm-3 is Optimum to: Reduce Specific On-Resistance Maintain Low Gate Oxide Electric Field 38

39 Buffered-Gate (BG) SiC Power MOSFET X1 = 0. 4 µm X2 is P+ Shielding Region Extension beyond Gate Edge Optimum X2 is 0.3 µm based on alignment tolerances 39

40 Buffered-Gate (BG) SiC Power MOSFET: Experimental Results 40

41 Buffered-Gate (BG) SiC Power MOSFET: Experimental Results TABLE I SUMMARY OF EXPERIMENTAL RESULTS FOR C-MOSFET, SG-MOSFET, AND BG-MOSFETS C- SG- BG- BG- MOSFET MOSFET MOSFET_L MOSFET_H Cell pitch [µm] BV [V] V th [V] R on,sp [mω-cm 2 ] C gd,sp [pf/cm 2 ] Q gd,sp [nc/cm 2 ] FOM <R on C gd > [mω-pf] x Improvement FOM <R on Q gd > [mω-nc] x Improvement K. Han, B.J. Baliga, and W. Sung, "A Novel 1.2 kv 4H-SiC Buffered-Gate (BG) MOSFET: Analysis and Experimental Validation", IEEE Electron Device Letters, Vol. 39, pp , February

42 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 42

43 SiC Power MOSFET: New OCTFET Cell Topology Conventional Split-Gate Buffered-Gate The New Octagonal Cell Topology for the SiC Power MOSFET (OCTFET) can be fabricated with the same process as the Conventional MOSFET. Gate Design is different during device layout. 43

44 SiC Power MOSFET: New OCTFET Cell Topology 44

45 1.2kV SiC Power OCTFET: Experimental Results Measured Performance of Devices fabricated at X-Fab Foundry 45

46 SiC Power MOSFET: New OCTFET Cell Topology TABLE I SUMMARY OF EXPERIMENTAL RESULTS FOR THE OCTFETS AND THE CONVENTIONAL LINEAR MOSFET linear_j0.7 O_J0.9 O_J1.1 O_J1.3 O_J1.5 O_J1.1_C CH. density [µm -1 ] JFET density BV [V] V th [V] *R on,sp [mωcm ] C gd,sp [pf/cm 2 ] Q gd,sp [nc/cm 2 ] FOM (Ron Cgd) [mω-pf] FOM (Ron Qgd) [mω-nc] * includes R sub (~0.7 mω-cm 2 ) 2.1x Improvement 1.4x Improvement K. Han and B.J. Baliga, The 1.2 kv 4H-SiC OCTFET: A New Cell Topology with Improved High- Frequency Figures-of-Merit", IEEE Electron Device Letters, Vol. 40, pp , February

47 Outline SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 47

48 BiDFET: Monolithic Bi-Directional FET 48

49 Proposed SiC Bi-Directional FET BiDFET Drain Metal Drain Metal Drain Metal 49

50 BiDFET: Experimental Results 50

51 BiDFET: Experimental Results 51

52 BiDFET: Experimental Results 52

53 BiDFET: Comparison with Prior Art Assumptions: Si Diode On-State Voltage Drop = 1.5 V Si Asymmetric IGBT On-State Voltage Drop = 2.0 V Si Symmetric (RB) IGBT On-State Voltage Drop = 2.5 V SiC Diode On-State Voltage Drop = 1.5 V SiC MOSFET On-State Voltage Drop = 0.25 V 53

54 BiDFET: Monolithic Bi-Directional FET B.J. Baliga and K. Han, "Monolithic SiC Bi-Directional Field Effect Transistor (BiDFET): Concept, Implementation, and Electrical Characteristics ", GOMACTech 2018, Paper 3.2, pp , March 13,

55 Conclusion SiC Power MOSFET Breakthroughs achieved at NCSU PRESiCE: SiC Power Device Manufacturing Technology SiC Power MOSFETs: Inversion Channel & Accumulation Channel The JBSFET: SiC MOSFET with Integrated Schottky Diode Split-Gate (SG) MOSFET: Improved HF-FOM Buffered-Gate (BG) MOSFET: Further Improved HF-FOM The OCTFET: A New Cell Topology with Superior High Frequency Figures-of-Merit The BiDFET: A Monolithic Bi-Directional Field Effect Transistor 55