Modeling the Influence of Dielectric Interface Traps on I-V Characteristics of TFETs
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1 Modeling the Influence of Dielectric Interface Traps on I-V Characteristics of TFETs Jie Min 1, Peter Asbeck UCSD 1 Present address: Global Foundries, Santa Clara, CA
2 Schematic TFET Structures Based on GaSb & InAs Planar (double gate) TFET i-inas Nanowire TFET p-gasb Wernersson et al n-inas
3 Schematic TFET Structures Based on GaSb & InAs Planar (double gate) TFET i-inas Nanowire TFET Defects cause significant nonidealities p-gasb Wernersson et al n-inas
4 Schematic TFET Structures Based on GaSb & InAs Planar (double gate) TFET i-inas Defects cause significant nonidealities Dielectric interface defects Nanowire TFET p-gasb Dielectric interface defects highlighted here Wernersson et al n-inas
5 Study Objective Provide simplified model to understand impact of individual interface traps on I-V characteristics of FETs Defect Effects SS degradation Vt Variability Low Frequency Noise Related Questions How to measure? How to minimize? Time, temperature dependence How bad relative to MOSFET?
6 Planar (Double Gate) TFET Simulation Electrostatics (fully depleted case) no defect Electrostatic potential along centerline Vds=.3V 15mV COMSOL V(x)~ ~Vo exp(-πx/λ)-vo
7 Planar (Double Gate) TFET Simulation Electrostatics (fully depleted case) no defect Electrostatic potential along centerline Vds=.3V 15mV Current Flow Follows Taur, Wu & Min, 215 COMSOL V(x)~ ~Vo exp(-πx/λ)-vo
8 Potential Perturbation Caused by Charged Defect Single Defect (charge=q) at dielectric/channel interface at distance x from junction Channel thickness: 5nm EOT: 1.2nm Charge q Electrostatic potential along centerline x=1.5nm x=4.5nm x=15nm 24mV 31mV COMSOL simulations
9 Potential Perturbation Caused by Charged Defect Single Defect (charge=q) at dielectric/channel interface at distance x from junction Channel thickness: 5nm EOT: 1.2nm Charge q Electrostatic potential along centerline x=1.5nm x=4.5nm x=15nm 24mV 31mV COMSOL simulations Green s Function (approximate) G xx (, ) t ε = q x x t / λ trap e = 2π x x (, ) ch V G xx t t Induced Potential (V) Analytical results 31mV Position (nm)
10 Potential for TFET with Interface Charges Conduction Band Energy (ev) q - q ideal Id (A) Id (A) q - q ideal Position (m) x 1-8 Channel Conduction Band With Defect Vgs Vgs (V) (V) Current for narrow strip (single mode)
11 Potential for TFET with Interface Charges Conduction Band Energy (ev) q - q ideal Id (A) Id (A) q + q ideal ideal - q Position (m) x 1-8 Channel Conduction Band With Defect Vgs Vgs (V) (V) Current for narrow strip (single mode) Double gate TFET Traps randomly distributed Positive and negative charged traps Energy (ev) Ideal Barrier Defect Potentials Total Potential
12 (c) Calculated Id-Vgs Characteristics Planar TFET with Dielectric Interface Traps 1 different random distributions considered for each number of traps Traps equally likely to be positive or negative (b) (a) Id (A) V gs (V) 1 trap 1 trap Nit=1.25e1 charges/cm V gs (V) 8 traps 8 traps Nit=1e11 charges/cm traps V gs (V) 4 traps Nit=5e11 charges/cm2 Double gate TFET dimensions: Lg=4nm Wg=1nm Variability in Vth Worsening of subthreshold slope
13 Histograms of Current at Different Bias Conditions 2 15 Double gate structure: ON Current (Vgs=.3V, Vds=.3V) 4 15 (a) V gs = V ds =.3V (b) (c) 4 traps 8 traps 35 V gs = V ds =.3V 4 traps 8 traps 1 trap 3 V gs = V ds =.3V 1 trap 25 1 Counts Counts V gs =.1V 4 V ds = traps.3v 4 traps Trap-free TFET current 5 I ds (A) Effect on ON current relatively small Double gate structure: OFF Current (Vgs=.1V, Vds=.3V) traps 1 trap V gs =.1V V ds =.3V 8 traps I ds (A) V gs =.1V V ds =.3V 1 trap I ds (A) I ds (A) Effect on OFF current dramatic Variation in current density I ds (A) I ds (A) Degradation in leakage current
14 At Id=1uA/um Interface Effects Considerations 1 defect 8 defects 4 defects Std dev Vgs 1.2 mv 8.7 mv 14.6 mv Subthreshold slope of Idave 28 mv/dec 32.2 mv/dec 66.5 mv/dec Std dev Vgs roughly follows N defects 1/2 Model: independent FET strips with varying Vt Average subthreshold slope degrades If ideal subthreshold slope increases with bias σ Vt =2mV σ Vt =1mV ideal Numerical simulation for gaussian variation of Vth
15 At Id=1uA/um Interface Effects Considerations 1 defect 8 defects 4 defects Std dev Vgs 1.2 mv 8.7 mv 14.6 mv Subthreshold slope of Idave 28 mv/dec 32.2 mv/dec 66.5 mv/dec Std dev Vgs roughly follows N defects 1/2 Model: independent FET strips with varying Vt Average subthreshold slope degrades If ideal subthreshold slope increases with bias Id (ua/um) MOSFET σ Vt =2mV 1-3 σ Vt =1mV Vgs(V) ideal Numerical simulation for gaussian variation of Vth
16 Nanowire Modeling Ideal Structure (fully depleted channel) V(x)~ Very good agreement with analytical model COMSOL electrostatics I-V analysis: 1D tunneling model Channel radius: 1nm Channel length: 1nm Results compare well with Lund University data IEDM 216 (ss down to 43 mv/dec) Only adjustable parameter: Vt shift
17 Electrostatics for Nanowire TFET with Defect x=4nm 3.2mV x=15nm 5.8mV Fully depleted channel assumed Potential evaluated along axis of nanowire Channel radius: 1nm Channel length: 1nm EOT: 1.5nm Peak potential change: 6mV (x5 lower than planar example) COMSOL simulation Analytical results 6 x 1-3 Approximate Green s Function Exact Green s Function 1 G r= r = kz kz (, ) sin ( ) sin ( ) s n n t π L n= 1 ( ) ( ) ( ) ( ) I kr K kr I kr K kr n tot n s n s n tot I ( ) ( kr ) I n tot Induced potential(v) mV r d = G( z, z r q 2 q ) = + ( z z q ) q exp( βrd 2πεα r 2 d / r ) q Position(m) x
18 Effect of Defect Potential on Nanowire Current 1-6 Simulated Id-Vgs Curves With Single Defect Charge q at 8nm 1-7 Id(A) q -q Memisevic &Wernersson Vgs (V) Experimental Imax/Imin=
19 MOSFETs vs TFETs Comparison of Effects of Interface Charges on Current Effect on Defect Charge on Conduction Band Energy in Channel Highest potential dominates Potential near tunnel junction dominates.2 Induced potential(v) Induced potential(v) Position(m) x Position(m) x 1-7 For MOSFETs, defects near center of channel are most important (For TFETs, defects close to tunnel junction are most important) Effect of Positive and Negative defects roughly symmetric with short channels <4nm Effect of Negative defects predominates in long channel devices Defect charges cause Vth variability but do not change subthreshold slope -.3
20 Relation to 1/f Noise 1/f theory: fluctuation of trapping/de-trapping in oxide traps S 2 q ktnbt Q = S id = S f κ di f / dq Q ( trap N bt : Oxide trap density, 1 19 /cm 3 /ev κ: Tunneling decay factor,~7 1 7 /cm 2 ) κ = Φ 2m B 2 This work provides estimate of di/dq trap (For fully depleted channel) 2
21 Relation to 1/f Noise 1/f theory: fluctuation of trapping/de-trapping in oxide traps S 2 q ktnbt Q = S id = S f κ di f / dq Q ( trap N bt : Oxide trap density, 1 19 /cm 3 /ev κ: Tunneling decay factor,~7 1 7 /cm 2 ) κ = Φ 2m B 2 This work provides estimate of di/dq trap (For fully depleted channel) Compare TFET and MOSFET assuming same value of S Q Data from Lund University One adjustable parameter to fit both simultaneously Hellenbrand, Wernersson et al 21
22 Summary & Conclusions Simple formalism allows computing effects of defects with fixed charge q along channel Variability in Vth Increase in subthreshold slope Subthreshold slope increase is unavoidable if Vth varies randomly (for TFET I-V curves) Cylindrical geometry appears to be more forgiving than planar geometry for same current Smallest possible EOT is beneficial Interface state densities should be reduced to below 1 1 to 1 11 cm -2 to avoid these effects Authors are grateful to Prof. Wernersson for making available some research results prior to publication
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