Fundamental Failure Mechanisms Limiting Maximum Voltage Operation in AlGaN/GaN HEMTs. Michael D. Hodge, Ramakrishna Vetury, and Jeffrey B.

Transcription

1 Fundamental Failure Mechanisms Limiting Maximum Voltage Operation in AlGaN/GaN HEMTs Michael D. Hodge, Ramakrishna Vetury, and Jeffrey B. Shealy

2 Purpose Propose a method of determining Safe Operating Area (SOA) of GaN Power Devices in a high voltage OFFstate. Describe fundamental failure mode limiting OFF-state SOA Describe a new test method to safely extract failure times for device operation close to catastrophic failure Discuss physical causal mechanisms of fundamental failure mode

3 Outline Introduction GaN Switch Operation Test Methodology Stress Observations Discussion of Observed Degradation SOA Prediction Summary

4 Introduction AlGaN/GaN HEMTs applications RF High Power RF Generation RF control High Frequency Power Management Acceleration factors defining SOA not completely understood Combination of temperature, voltage, current, and RF Dominant failure mechanisms in OFF-state not well understood in literature Development stress methods close to catastrophic failure

5 GaN Material Advantages Ruggedness Power Handling Low Loss, Low Noise UNREALIZED Potential

6 Reported Reliability Failure Mechanism in GaN HEMTs Related to Inverse Piezoelectric Effect (IPE) Hot Electron Induced Degradation (HEI) Requires High electric field Process related pits? Impact Physical defect (crack or surface pit) Symptoms R ON, I DMAX, I DSS, G m, I G Questions Time dependence not completely understood Requires Hot electrons Impact Create traps in buffer and/or barrier layers Symptoms R ON, I DMAX, I DSS, G m, I G Questions Trap parameters not complete defined

7 Experimental Device AlGaN GaN Switch Source Connected FP Source Connected FP Source Sourc e SiN L GS Gate Gate L G SiN L DS PA FET L GD AlGaN/GaN PA FET Drain Drain Source SiN Gate L GS L G L DS SiN L GD AlGaN/GaN Switch FET Drain AlGaN/GaN PA FET Asymmetric Device Gate off-center in channel Lgs<Lgd Source connected FP AlGaN/GaN Switch FET Symmetric Device Gate centered in channel Lgs=Lgd No Field Plating

8 Switch Operation V BD V SOA V G V TH I DS I DS V G = 0V OFF-State V GS ON-State V DS DC bias only applied to gate terminal Used to control device state OFF-State Gate is biased far away from V TH Ensure device does not cross V TH or exceed SOA over range of RF swing ON-State No bias on Gate FET is fully ON FET sized to remain in linear region over RF swing

9 OFF-State - Safe Operation Limits I DS A SOA Limit V BD V SOA V G V TH L DS Technology Limit OFF-State V GS B C Red Line Catastrophic breakdown for a given layout Blue Line SOA for a given channel geometry V DG

10 Drain Current Current Voltage Test Method LV MV HV Compliance Voltage SPA Set Current Actual FET Leakage Low Voltage Med Voltage Close to V BD V G <V TH Drain Voltage Time Semiconductor parametric analyzer (SPA) set to forced current mode. Voltage compliance set to desired stress value Forced current set just above device leakage for a given voltage. As determined by characterization. SPA increases voltage to achieve set current Voltage compliance is reached and SPA fixes voltage.

11 Experimental Summary Constant Voltage Stress Via SPA forced drain current mode Protects device from catastrophic breakdown Allows stress close to device breakdown Stress Conditions V GS = -10V V DS Compliance = 180V - 205V T = 1 hour intervals ON-State Characterization R ON, I DSS, I DMAX Measured at 5 points of interest OFF-State Characterization V BD Performed before and after each stress

12 Stress Observations Breakdown Voltage Walk-out Phenomena Initial Walk-out V GS =-10V 1 Walk-out 2 Breakdown voltage walk-out Voltage required for given OFF-state drain current increases Reported in literature in GaAs MESFETs 1 and phemts 2 Attributed to trapped carriers in gate-drain region. 1) P. Ladbrooke et. al. IEEE Trans. Electron Devices, 35(3), March 1988, pp ) P. Menozzi et. al. IEEE Trans. Electron Devices, 43(4), April 1996, pp

13 Stress Observations Breakdown Voltage Walk-in Phenomena Walk-out Walk-in V GS =-10V 3 Walk-in 2 Breakdown voltage walk-in Voltage required for given OFF-state drain current decreases Similar in behavior observed literature on GaN PAs 1,2 1) D. Marcon et. al., 2010 IEEE Electron Devices Meeting (IEDM), San Francisco CA, Dec. 2010, pp ) M. Meneghini et. al., IEEE Electron Devices Meeting (IEDM), Washington DC, Dec. 2011, pp

14 Drain Current (ua/mm) [Vd=165V] Drain Voltage (V) [Id=100 ua/mm)] Walk-out and Walk-in Time Dependence Walk-out Walk-in Time (Hours) Evolution of walk-out and walk-in over time

15 In-situ Terminal Leakage Currents E Walk-out Walk-in D A B C 190V 200V 205V Dominant Leakage path is drain to gate After T=10 Hours source leakage increases Compliance Voltage Data suggests a degradation of gate Schottky diode

16 Drain Current (ua/mm) OFF-State Breakdown Voltage Characterization Initial 15 Final 14 Walk-out Walk-in Drain Voltage (V) OFF-State characterization around key stress points Clear evidence of walk-out and walk-in phenomena

17 Gate Current (ua/mm) Drain Current (ua/mm) OFF-State Breakdown Voltage Characterization IG VDS=20V IG VDS=165V ID VDS=20V ID VDS=165V Time (Hours) OFF-State Characterization leakage current at V DS =20V and V DS =165V T=10 Hours leakage at high bias increases T=15 Hours leakage at low bias increases

18 Gate Current (ua/mm) Drain Current (ma/mm) ON-State Characterization V GS -I DS Sweep Observations Significant change to sub-threshold leakage Increase two orders of magnitude once stress I DS increases. Possible degradation of gate diode. Minimal change in ON-State. ON-state parametric change <7%. Gate Voltage (V)

19 Gate Current (ua/mm) Drain Current (ma/mm) Gate Current (ua/mm) Drain Current (ma/mm) ON-State Time Dependence IG VGS=-8V ID VGS=-8V Time (Hours) Observations Subthreshold shows clear walk-out and walk-in signature. Small change in ON-State I DMAX decreases by < 4% I G leakage increases uniformly over bias IG VGS=1V ID VGS=1V Time (Hours)

20 Drain Leakage (ua/mm) Gate-Drain/Source Diode Characterization V GS =-10V Gate-Drain (Pre-Stress) Gate-Drain (Walk-out) Gate-Drain (Walk-in) Gate-Source (After Gate-Drain Walk-in) Drain Voltage (V) Test Sequence 1. OFF-state characterization 2. Gate-Drain diode stressed to walk-in 3. OFF-state characterization Observation 1. Gate-Source diode unchanged 2. Gate-Drain diode changed Conclusion 1. Damage localized to Gate-Drain region.

21 Motivation to Determine SOA A SOA Limit L DS Technology Limit B C V DG Voltage stress leads to loss of gate control Evidenced by increase in leakage current Preliminary PEM images reveal localized hot spots along gate. Necessary to determine time dependence of failure versus applied voltage. Will lead to the determination of actual SOA (Blue Line/Region)

22 Voltage Acceleration - Literature (1) (2) 1. Dieci et. al. on Commercial GaAs HFETs OFF-State stress reveals a V DG threshold Below V DG threshold device lifetimes very high Based on a derived physical model FOM 2. Marcon et. al. on GaN-on-Si HEMT PA TTF vs Applied Voltage follows a power law trend 1) D. Dieci et. al., IEEE Trans. Electron Device, 48(9), Sept. 2001, pp ) D. Marcon et. al., 2010 IEEE Electron Devices Meeting (IEDM), San Francisco CA, Dec. 2010, pp

23 Physcial Model FOM Determination of SOA in GaN RF Switches VDG (V) FOM = t F * Ig 1/2 [h*(ua/mm) 1/2 ] GaN RF Switch FOM Definitions t F = time to walk-in (hours) Ig = Average of the magnitude of gate leakage (ua/mm) Preliminary results are similar to Dieci et al. Suggests a threshold acceleration based on V DG

24 Conclusions Method of OFF-State stress close to catastrophic breakdown proposed. Observation of two distinct mechanisms Breakdown voltage walk-out Breakdown voltage walk-in Degradation appears to be limited to OFF-State parameters Appears linked to gate diode Schottky properties Further experimentation shows damage is located on stressed side of gate diode. By varying the stress voltage a V DG acceleration factor can be determined