High Voltage Normally-off GaN MOSC- HEMTs on Silicon Substrates for Power Switching Applications

Transcription

1 High Voltage Normally-off GaN MOSC- HEMTs on Silicon Substrates for Power Switching Applications Zhongda Li, John Waldron, Shinya Takashima, Rohan Dayal, Leila Parsa, Mona Hella, and T. Paul Chow Department of Electrical, Computer, & Systems Engineering This work was supported by SRC (Task ) and NSF ERC on Smart Lighting (EEC ), and made use of ERC Shared Facilities supported by the NSF under Award Number EEC Rensselaer Polytechnic Institute Troy, NY USA

2 Outline Introduction Design and Fabrication of the GaN MOS Channel HEMTs on Silicon Substrate Experimental DC Characteristics Circuit Results Simulation of a Buck-Boost Converter Experimental Demonstration of GaN MOS Bidirectional Switch on Silicon Substrate Zhongda Li 2 CFES Annual Conference 2013

3 Introduction GaN has been very attractive for power switching applications 10x critical field compared with silicon Up to 200 o C operation temperature 2D electron gas (2DEG) with mobility up to 2000cm 2 /V-s GaN MOS channel devices (MOSFETs and MOS Channel HEMTs) has the advantages of Normally-off operation Absence of gate turn-on Low gate leakage Zhongda Li 3 CFES Annual Conference 2013

4 GaN MOS Channel HEMTs Source UID GaN Al 0.25 Ga 0.75 N Gate MOS channel UID GaN 2DEG AlN/GaN Buffer Silicon Drain The GaN MOS channel HEMTs (MOSC- HEMTs) were the combination of the GaN HEMTs and GaN MOSFETS The drift region utilized the highly conductive 2DEG similarly as in GaN HEMTs The MOS channel was formed by etching off the AlGaN to remove the 2DEG under the gate Deep submicron (0.3 µm) MOS channel was used in order to reduce its resistance component The use of the silicon substrate greatly improved the cost-effectiveness of this GaN device Zhongda Li 4 CFES Annual Conference 2013

5 Design of the GaN MOSC-HEMTs Source Source Device on Epi A Gate UID GaN Al 0.25 Ga 0.75 N UID GaN AlN/GaN Buffer Silicon Device on Epi B Gate Al 0.25 Ga0.75 N UID GaN CF 4 plasma treated Al 0.10 Ga 0.90 N Drain Drain Two commercial GaN-on-Si epis were used in fabricating the GaN MOSC-HEMTs Epi A has a optimal 20 nm thick GaN cap, but a thin total epi thickness of 1.8µm which limits the vertical BV Epi B has 1 nm GaN cap which was insufficient in achieving good RESURF effects, and a thicker total epi thickness of 4 µm Due to the difference in GaN cap, different designs were used on the two Epi AlN/GaN Buffer Silicon Zhongda Li 5 CFES Annual Conference 2013

6 RESURF Effects from the GaN Cap Fixed Charges in the Drift Region GaN AlGaN GaN (+Qpas) (- Qpol 2) (+Qpol 2) (- Qpol 1) (+Qpol 1) (- Qpol 2) - Qf +Qf Passivation The 20nm GaN cap on Epi A provided net negative polarization charges (-Q f ) at the top GaN/AlGaN interface which balanced the net positive polarization charges (+Q f ) Electric field lines (perpendicular to equivalent potential lines) terminate on the negative charges at the Qf, n+ Si substrate, and the gate electrode. Zhongda Li 6 CFES Annual Conference 2013

7 Breakdown Simulations: GaN MOSC-HEMTs on Epi A At BV=40V, without GaN cap Oxide Field along Surface At BV=646V, with GaN cap Oxide Field along Surface Numerical simulations (MEDICI) showed a higher BV and a much better RESURF effect, with low gate corner field and a more uniform surface field Zhongda Li 7 CFES Annual Conference 2013

8 Breakdown Voltage (V) Breakdown Simulations: GaN MOSC-HEMTs on Epi B At BV=40V, without GaN cap Oxide Field along Surface Fixed Charges in the Drift Region AlGaN GaN (+Qpas) (-Qpol 1) (+Qpol 1) (- Qpol 2) +Qf Passivation At BV=646V, with GaN cap Oxide Field along Surface BV overall BV GaN 0 0.0E E E E E+12 Total Charges (cm-2) Limited by gate oxide breakdown For devices on Epi B, the 1 nm GaN cap was insufficient in inducing negative polarization charge Thus the high oxide field at the gate corner can limit the overall BV of the device The total fixed charges (+Q f ) needed to be reduced, here by means of incorporation of negative fluorine ions into the AlGaN using CF 4 plasma treatment Zhongda Li 8 CFES Annual Conference 2013

9 Device Fabrication 0. Starting material 1. Mesa isolation 2. Epi B: CF 4 plasma treatment 3. Deposit and pattern field plate oxide Zhongda Li 9 CFES Annual Conference 2013

10 Device Fabrication (Continued) 4. Etch recess MOS channel 5. Sputter and pattern polysilicon gate 6. Deposit ILD and lift-off Ti/Al/Ni/Au ohmic metal 7. Evaporate and pattern Ti/Al final metal Zhongda Li 10 CFES Annual Conference 2013

11 Experimental DC Characteristics Output I DS -V DS on Epi A Output I DS -V DS on Epi B ID (ma/mm) V G =15V, step= -2V ID (ma/mm) V G =13V, step=-2v VD (V) VD (V) The GaN MOSC-HEMTs on Epi A with 0.3 µm MOS channel and 8 µm drift length showed a threshold voltage of +0.5V, and best R on,sp of 4.05 mω-cm 2, which was among the lowest reported values for normally-off GaN MOSC-HEMTs. The GaN MOSC-HEMTs on Epi B with the same dimensions showed higher R on,sp of 35 mω-cm 2, which was attributed to a lower MOS channel mobility caused by the rougher GaN surface Zhongda Li 11 CFES Annual Conference 2013

12 Analysis of Specific On-Resistance MOS channel Drift Access Contact μ (cm 2 /V-s) N (cm -2 ) 1.10E E E+12 - R sh (Ω/sq.) 1.03E E E+03 - L (μm) W (μm) R (Ω) R on Percentage 12% 36% 43% 9% R on,sp ( mω-cm 2 ) 4.05 Zhongda Li 12 CFES Annual Conference 2013 Ron,sp (mω-cm 2 ) MOSC-HEMT(with GaN Cap Layer) MOSC-HEMT(without GaN Cap Layer) HEMT This work, SiO2 MIT, Al2O3 [8] Furukawa & RPI, SiO2 [4] RPI, SiO2 [2] Channel Length (µm) The analysis of the resistance components of the 4 mω-cm 2 device showed that with the deep submicron channel design, only 12% of the total resistance came from the MOS channel The experimental results were consistent with those from the numerical simulation when scaling down the MOS channel, showing that the GaN MOSC-HEMTs were able to achieve comparable R on,sp to that of GaN HEMTs

13 Current (ma/mm) Experimental Breakdown Characteristics: Epi A (20nm GaN Cap) ID, 20um IG, 20um ID, 8um IG, 8um VD (V) On Epi A, a non-destructive breakdown voltage of 350 V was measured, regardless of the drift lengths of the device (8 µm to 20 µm) This indicated that the breakdown voltage was limited by vertical breakdown voltage of the epi due to the thin total epi thickness I D increased sharply at BV while I G stayed the same, indicating that the breakdown happened in the bulk of the semiconductor near the drain side instead of at the gate corner The low gate field design enhanced the robustness of the device Zhongda Li 13 CFES Annual Conference 2013

14 Current (ma/mm) Experimental Breakdown Characteristics: Epi B (CF4 Treated) ID IG VD (V) Devices fabricated on the thick GaN epi (epi B) without CF 4 plasma treatment showed a BV of only 40 V regardless of drift length Devices with 20 µm CF 4 -plasma-treated drift region showed a BV of 840 V However, the breakdown happened at the gate corner and thus was destructive, due to the less effective RESURF effects from the CF 4 plasma treatment compared with the thick GaN cap Zhongda Li 14 CFES Annual Conference 2013

15 Specific On-resistance (mohm-cm 2 ) R on,sp vs. BV D Si Limit This work Furukawa/ RPI '10 Furukawa'11 NEC'09 MIT'10 Toshiba'07 Projected perfornance with thick GaN epi or 1D 2H-GaN other techniques Limit Breakdown Voltage (V) The R on,sp vs BV plot of this work exceeds the silicon limit, but is not as good as the state-of-the-art performances due to the BV limitation of the thin GaN epi thickness Higher BV up to 1200V has been projected from numerical simulations with thick GaN epi layers or other BV enhancement techniques Zhongda Li 15 CFES Annual Conference 2013

16 SPICE Simulation of a Buck-Boost Converter using GaN MOSC-HEMT SPICE model of the GaN MOSC-HEMT were extracted from MEDICI simulations and used in buck-boost converter simulations, projecting system efficiency of 90% with ideal inductors Device optimization at 10 MHz Power stage efficiency Zhongda Li 16 CFES Annual Conference 2013

17 GaN MOS Bidirectional Switch on Silicon Substrate We have also demonstrated a GaN MOS bidirectional switch on silicon substrate using the GaN MOSC-HEMTs fabricated on Epi A G V G G D S S D V+ D1 V A D2 V- GaN bidirectional switch operation: On-state: (V G >V TH ): Both D1 and D2 are on, switch conducts bidriectionaly Off-state (V G <V TH ): With V- grounded and positive V+ increasing, D1 is always off but D2 will be on after V A floats to be higher than V TH D2 only support V TH and D1 supports rest of the voltage Zhongda Li 17 CFES Annual Conference 2013

18 Current (ma) Current (µa) GaN MOS Bidirectional Switch on Silicon Substrate Bidirectional Conduction I-V Bidirectional Blocking I-V 5-2V 0V 4 2V 4V 3 6V 8V 2 10V 12V Bias Voltage (V) -10 Bias Voltage (V) The on-resistance of the AC switch is twice of the single device, and the blocking capability up to 200V Zhongda Li 18 CFES Annual Conference 2013

19 Id (ma/ mm) Id (ma/ mm) Id (ma/ mm) Id (ma/ mm) GaN MOS Channel FinFETs Lc 300nm : without Lc=0.3um Fin structure V G =-2 to 7V Step=1V Lc 300nm : Lc=0.3um with Fin structure V G =-2 to 7V Step=1V Fins Source Recess etch Drain Vd (V) I D -V G : without Fin structure 300 Lch=1.1um 250 Lch=0.8um Lch=0.6um 200 Lch=0.4um Lch=0.3um 150 Lch=0.2um Vd (V) I D -V G : with Fin structure 160 V D =10V 140 Lch=1.1um Lch=0.8um V D =10V 120 Lch=0.6um 100 Lch=0.3um Vg (V) Vg (V) *Shinya Takashima et al, to be published Zhongda Li 19 CFES Annual Conference 2013

20 Summary We have designed and fabricated GaN MOS Channel HEMTs with deep submicron MOS channels on silicon substrates on two different epi layers Best specific on-resistance of 4 mω-cm 2 Breakdown voltage of 350V on Epi A limited by the epi thickness, and 840V on Epi B which has a thicker GaN epi A buck-boost converter has been simulated using SPICE parameters of the device A GaN MOS bidirectional switch on silicon substrate has also been demonstrated Zhongda Li 20 CFES Annual Conference 2013

21 Thank you! Zhongda Li 21 CFES Annual Conference 2013