GaN HEMT SPICE Model Standard for Power & RF. Samuel Mertens Si2Con San Jose, CA October 6, 2015
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1 GaN HEMT SPICE Model Standard for Power & RF Samuel Mertens Si2Con San Jose, CA October 6, 2015
2 Compact Model Standardizing Compact Models Since 1996 Started with BSIM3 Support standardization and making the model usable by industry GaN HEMT first foray into III-V semiconductors Cadence Design Systems, Inc..
3 CMC Progress Chart Plot courtesy of Green Cadence Design Systems, Inc..
4 HEMT vs MOSFET (really old) view HEMT Schottky gate M-S 2DEG III-V or II-VI Always on (gate turns device off) Only n-channel Expensive Reliability issues Trapping important G S D Metal stack MOSFET MOS-gate Si/SiO2 Inversion layer Si Easy control of Vth N- and p-channel (CMOS) Inexpensive Reliable No issues with traps G S D Cadence Design Systems, Inc..
5 HEMT vs MOSFET how it is now HEMT Schottky gate M-S or M-I-S (using deposition) 2DEG MOSFET High K-dielectric gate (not SiO2) using deposition Inversion layer III-V or II-VI Si or combination with (Ge or C) Depletion mode and Enhancement mode possible N-channel, no good p-channel Expensive, but cost is improving Reliability concerns but improving Traps still an issue Easy control of Vth N- and p-channel (CMOS) Inexpensive (but not for small volume) Reliable, but is more of a concern No issues with trapping (except for LDMOS aging) S G S G D D Cadence Design Systems, Inc..
6 GaN vs Si GaN higher bandgap (3.4 ev) than Si Very high critical field which enables a much smaller on-resistance (shorter drift region) S G Ld D Cadence Design Systems, Inc..
7 GaN vs Si 2DEG HEMT structure and GaN material properties allow for high electron mobility and current in GaN HEMTs Thermal conductivity similar to Si GaN can operate at higher temperatures Cadence Design Systems, Inc..
8 Historically, III-V semiconductors used to live only live in RF Higher Electron-mobility at high electron density of III-V (including GaN) leads to higher operational frequencies and lower losses Not negligible market-wise GaAs PA are part of most cell phones The complexity of the chips are smaller Main simulation focus is in frequency domain Cadence Design Systems, Inc..
9 III-V industry has been relatively free of standard models Historic reasons In-house fabrication Small # of transistors Frequency domain Proprietary models Based on public model, but with improvements Considered a competitive edge Limited tools needed Cadence Design Systems, Inc..
10 GaN in Power Electronics since 2009 Reduced power losses for switching applications Low gate charge, and low on-resistance lead to many commercial application for power conversion (and no QRR) These companies are used to Si integration and Si flow Standard models are part of that flow Time domain is important No body no inversion, no accumulation can t use Si model Cadence Design Systems, Inc..
11 Compact Model primer Types of models considered 1. Empirical Mathematical functions are fit to the I-V and Q (or C)-V measurements 2. Threshold Voltage based Physical behavior of I-V and Q-V are fit to functions, derived from approximate solution of the underlying physics, using the threshold voltage as a fitting parameter 3. Surface-Potential (or charge-based current) based Surface-Potential (or charge) is calculated out of which currents and charges are derived Cadence Design Systems, Inc..
12 CMC standardization procedure Four phases 1. Call for models 2. Self-Evaluation 3. Evaluation by CMC members 4. Prepare Standard Cadence Design Systems, Inc..
13 Phase 1 details CMC compiled a list of requirements Technical requirements Support requirements We received 9 applications who returned a checklist and a list of references Committee reviewed the applicants Cadence Design Systems, Inc..
14 Phase 1 requirements - highlights Technical requirements Physical Surface-Potential based (preferred) Gummel-symmetry Support requirements Documentation Support Maintenance Cadence Design Systems, Inc..
15 Phase 1 progress 8 were invited to present at the Q4 13 CMC meeting Anwar (Uconn), Angelov (Chalmers), Antoniadis (MIT), Chan(UST), Khandelwal (UNIK), Martin (LETI), Shur (RPI), Trew (NCSU) 4 candidates found a sponsor to move to next phase Cadence Design Systems, Inc..
16 Phase 2 candidates Angelov (Chalmers) Semi-empirical, semi-threshold voltage based Current standard in RF Antoniadis/Radhakrishna - MVSG (MIT) Charge-based current calculation Khandelwal ASM-HEMT (UNIK) Surface Potential based Martin HSP (LETI) Surface Potential based Cadence Design Systems, Inc..
17 Phase 2 details Two sets of measurement data were supplied Qorvo (RF) Toshiba (Power switching) The 4 candidates were asked to fit this data to their model and then show overlays for a list of plots Cadence Design Systems, Inc..
18 Phase 2 ballot results After ballot 2 candidates are being reviewed by CMC membership in phase 3 Antoniadis/Radhakrishna MVSG (MIT) Khandelwal ASM-HEMT (UNIK) Really strong candidates for both RF and power switching applications Cadence Design Systems, Inc..
19 Phase 2 data RF (Qorvo) DC I/V Pulsed I/V S-parameters Power Sweep Load Pull/Source Pull Cadence Design Systems, Inc..
20 Pulsed I-V Pulsed I-V measures I-V using short pulses starting from a quiescent operating point Allows one to measure effect of selfheating and trap states Self-heating is important at high drain voltage/current Traps (depend on the bias condition) affect the output characteristics and cause the knee walkout Cadence Design Systems, Inc..
21 Knee walk-out RF device DC I-V and pulsed data 5 V and 10 ma/mm Plots courtesy of Radhakrishna 20 V and 100 ma/mm Cadence Design Systems, Inc..
22 S-parameters Plots courtesy of Khandelwal Cadence Design Systems, Inc..
23 RF measurements power sweeps Plots courtesy of Radhakrishna Cadence Design Systems, Inc..
24 Source sweep Plots courtesy of Khandelwal Cadence Design Systems, Inc..
25 Phase 2 data Power switching (Toshiba) DC I/V vs. Temperature C/V Switching Collapse Gummel symmetry/mcandrews Symmetry test Cadence Design Systems, Inc..
26 On-resistance vs. Temperature Plot courtesy of Khandelwal Cadence Design Systems, Inc..
27 Capacitances vs. Voltage Plot courtesy of Radhakrishna Cadence Design Systems, Inc..
28 Switching collapse characteristics definitions Plots courtesy of Radhakrishna Cadence Design Systems, Inc..
29 Switching characteristics T= 25 C f= 10 KHz f= 5 KHz f= 1 KHz f = 10KHz Device breakdown at 320V beyond 40C Plots courtesy of Radhakrishna Cadence Design Systems, Inc..
30 Gummel Symmetry - Toshiba Plots courtesy of Khandelwal Cadence Design Systems, Inc..
31 Phase 3 CMC members received Model code (Verilog A) Documentation Extraction procedure Parameters sets Testing model Ballot (Q2 16) Cadence Design Systems, Inc..
32 Phase 3 testing Extraction on their own devices Circuit simulation Larger circuits Convergence Performance Time and Frequency domain Noise testing Usability Cadence Design Systems, Inc..
33 Phase 4 Model is made ready for standardization QA suite OP parameters Clean up Clear final code Could take 1-2 quarters Standard model at end of Cadence Design Systems, Inc..
34 CMC Join CMC to help us define this standard Cadence Design Systems, Inc..
35 Acknowledgements All model candidates for their hard work Ujwal Radhakrishna (MIT) and Sourabh Khandelwal (UCB) for letting me share their plots CMC members Qorvo and Toshiba for the HW data James Fiorenza (ADI), Vijay Krishnamurthy (TI) and Rob Jones (Raytheon), Keith Green (TI) Cadence Design Systems, Inc..
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