How to Design Power Electronics

Transcription

1 How to Design Power Electronics The HF in Power Semiconductor Modeling and Design September 3, 2015 Ingmar Kallfass Institute of Robust Power Semiconductor Systems University of Stuttgart

2 Outline Semiconductor-Based Power Electronics An Introduction Challenges in Power Module Design Power Module Design Flow Modeling and Characterization Electro-Thermal Co-Simulation GaN Integration: Power Electronic Circuits 2

3 SEMICONDUCTOR-BASED POWER ELECTRONICS AN INTRODUCTION 3

4 Power Where Power Electronics meet Microwaves Semiconductor Technologies Scaling & Device Engineering Silicon IGBT MOSFET vs. Compounds SiC MOSFET/IGBT GaN HEMT Performance Maturity & Reliability Cost Share of Markets and Applications Compounds GaAs/InP HEMT/HBT GaN HEMT vs. Silicon MOSFET SiGe HBT Frequency 4

5 Power Electronics A Definition Power Electronics is the extension of solid-state electronics away from handling communications and data and into the business of efficiently handling power, from milliwatts to gigawatts. It makes the mobile phone battery last longer, it makes hybrid cars practicable, and it helps make electrical generation and distribution possible from sources ranging from a solar cell on your roof to a nuclear reactor in mainland Europe. [BIS] 5

6 Power Electronics A Definition Power Electronics is (...) an enabling technology that often determines the performance of, and provides the competitive advantage for, much more expensive devices or systems. For example, choosing a mobile phone or lap-top computer for its battery life is actually a Power Electronics decision, with the battery performance itself just one part of that. The importance of Power Electronics to the economy is consequently very much greater than its direct market value. Power Electronics is rarely seen as an end product by the general public, but it does play a critical role in almost all aspects of our daily lives. [BIS] 6

7 Applications and Technologies Source: GaN-on-Si power transistors from French lab Leti, CEA-Leti 7

8 Power Semiconductor Figures of Merit Johnson FOM describes the capability of power handling at high frequencies Baliga FOM describes the capability of minimizing on-state power loss in a transistor switch, i.e. loss due to current flow through on-resistance 8

9 Power Semiconductor Figures of Merit Switching loss power as function of transistor area (simplified) Minimum switching loss Semiconductor-related loss term (= FOM) 9

10 FOM Power Semiconductors [Catrene] 10

11 SEMICONDUCTOR-BASED POWER ELECTRONICS CHALLENGES IN POWER MODULE DESIGN 11

12 efficiency [%] Power Conversion: Small and Light, but also Efficient, Robust and EM Compatible power density [W/cm 3 ] 12

13 ECPE* Technology Roadmap Requirement size weight efficiency cost robustness Key Performance Indicator power density [kw/l] power-to-mass ratio [kw/kg] efficiency [%] relative cost [kw/ ] failure rate [1/h] Goal: Improvement by 2020 by a factor of W DC-DC PSiP 24 W/cm 3 65 W [golem.de] *European Center for Power Electronics 13

14 Design Measures in Switched-Mode Converters Control Filters (Passives) Transistor Power Switches Reduction of Related entities Measures Size, weight of passives high f sw Transistor switching loss Parasitic LC resonance (gate and power loops) Cooling effort EMC shielding/filtering small FOM = R on Q sw high d/dt slopes compact layout & high integration density high temp. operation of wide-bandgap SC EMC-oriented design 14

15 Tradeoffs size f sw d/dt high T operation integration density weight efficiency cost robustness EMC Optimum design requires an RF-refined design flow from device characterization and modeling to multi-domain circuit analysis 15

16 Multi-Domain Modeling & Design Characterization Modeling Design IV CV QV vs Temperature LF dispersion Thermal impedance B1506A Modeling Transistor Package DBC, PCB static dynamic thermal time and frequency domain analysis electro-magnetic simulation C th,j R th,jc electro-thermal co-simulation C th,hs R th,hs 16

17 POWER MODULE DESIGN FLOW MODELING AND CHARACTERIZATION 17

18 Refining a (Transistor-)Switch Model 2 dim. f(v) NQS LF dispersion 1 dim. f(v) R on Caps I ds /g m gate IV (HEMT) bulk IV (MOSFET) electrothermal RF parasitics (package) overtly simplistic high fidelity 18

19 Dynamic IV for Switching of Inductive Loads I d VDS ID 3 2 Vin IdMAX VG t PLOSS 1 V ds VG V Plateau t cross ON t ON t cross OFF t Gate charge is required for the calculation of switching loss and efficiency 19

20 Dynamic IV for Switching of Inductive Loads Dynamic IV in a FET transistor switch transits from sub-threshold to saturation to linear regime 20

21 Capacitance (pf) Conventional Capacitance Measurement DUT: SiC MOSFET 600V, 100mΩ, 35A Ciss Coss Crss B1506A Vds (V) measurement conditions as defined in datasheets Vgs = 0 V Vds = 0 to 500 V f = 100 khz Q derived from capacitance: 21

22 Capacitance Trace for Inductive Load Switching datasheet application C gs [ff/0.1mm] C gd [ff/0.1mm] GaAs 0.15µm RF power phemt 22

23 Vgs (V) Qg Measurement Qg HC Qg HV DUT: Si MOSFET 100V, 11mΩ, 200A JESD24-2 standard Qg (nc) Measurement setup: Ig = 5mA HC meas: Vdsoff=60V Idson=10A HV meas: Vdsoff = 100V B1506A Capacitance derived from Q: 23

24 Traps in GaN Devices well known from RF devices drain-lag / gate-lag LF dispersion dynamic R on after OFF-to-ON switching, R on remains high for a period of time trapping time constants from ns to ms or even longer (continuous exposure) [Catrene] 24

25 Dynamic Ron Measurement V stress V ds, I d 1 3 I d 3 Meas Meas 2 1 V ds V low V on t stress t delay1 2 t Quiescent V stress Vds_Pulse Vgs_Pulse total delay V ds pulse width V gs pulse width T_delay1 for safety. Minimun value depends on slew rate of drain SMU Very short total_delay necessary for measuring dynamic effects V ds pulse delay V gs pulse delay t 25

26 Id (A) Trapping Effects in GaN devices Effect of V stress in Output Characteristics DUT: 600V GaN-on-Si trapping states in the off-state affect R on in the on-state V_Stress = 50V V_Stress = 100V V_Stress = 150V V_Stress = 200V Vds (V) Measurement Setup VdsPulse_Delay = 1us VdsPulse_width = 10us VgsPulse_Delay = 1.6us VgsPulse_Width = 8us Period = 2ms NOS = 1 26

27 Ron (Ω) R on vs. Time V stress = 200V SMU slew rate delay stable voltages? DUT: 600V GaN-on-Si V stress = 20V Measurement Setup VdsPulse_Delay = 1us VdsPulse_Width = 10us VgsPulse_Delay = 1.5us VgsPulse_Width = 8us Period = 2ms NOS = 1 Resolution=200ns E+00 1.E-06 2.E-06 3.E-06 4.E-06 5.E-06 Time (seconds) 27

28 Id (A) Benchmarking Different GaN Devices Device A Device B Device C comparable devices from different manufacturers Measurement setup Same voltage conditions VdsPulse_Delay = 1us VdsPulse_Width = 10us VgsPulse_Delay = 1.5us VgsPulse_Width = 8us Period = 2ms NOS = Vds (V) 28

29 Ron (Ω) R on Temperature Dependence B1506A w/ heat plate T=23 C T=100 C T=150 C DUT: SiC MOSFET 600V / 100mΩ / 35A Vgs=10V Ids (A) Measurement Setup Vgs=10V GatePulse_Delay=100us GatePulse_Width=100us DrainPulse_Delay=0us DrainPUlse_Width=200us PulsePeriod=50ms 29

30 Model Requirements 2D Capacitance Model LF Dispersion Model Thermal Model 30

31 POWER MODULE DESIGN FLOW ELECTRO-THERMAL CO-SIMULATION 31

32 SiC MOSFET Multi-Chip Power Module AlN DBC with half- and full-bridge bare-die SiC MOSFETs driver ICs bootstrap supply buffer caps f sw > 100 khz power up to 10 kw Reliability: 10 C simulated ΔT from T j to T heatsink 32

33 Electro-Thermal Co-Simulation Operating the Full-Bridge Module as a DC-AC Inverter f sw = 100 khz Alternating output voltage V P = 340 V Alternating output current I P = 11 A Alternating output power HB1 HB2 Temperature transients R th heatsink: K/W 33

34 Fullbridge Module Transient Simulation Observations The temperature in the SiC MOSFETs pulsates with 60 Hz Temperature difference about 5 C Temperature peaking is only visible in the junction layer Time constants of the materials are high enough 34

35 Electro-thermal Co-Simulation M2 M1 Mold mass 1 mm Bond-hor. Bond-vert. 0.5 mm Al-Top 0.04 mm SiC 0.4 mm Solder 0.1 mm Cu (DBC) 0.3 mm Ceramic (DBC) 0.63 mm Cu (DBC) 0.3 mm Heatsink 2mm New degrees of freedom Thermal equivalent circuit extraction (thermal impedance) Optimized compact layout of modules (hybrid, multi-chip, on-chip) Reduction of safety margins (de-rating) Robustness-oriented design Lifetime prediction (coupling to thermo-mechanical co-simulation) 35

36 POWER MODULE DESIGN FLOW GAN INTEGRATION 36

37 AlGaN/GaN HEMTs V E-(GI)HEMT 600V E-mode Si/GaN cascode 650V E-HEMT 600V E-HEMT 600V D-HEMT can be tailored for power (Baliga FOM, R on Q g, V bd ) and microwave applications (Johnson FOM, f max, V bd ) show best R on Q g compared to Si and SiC can be cost-efficient when on Si-substrate as lateral devices are amenable to monolithic functional integration are today less mature (traps -> reliability, dynamic R on,...) are intrinsic depletion-mode / normally-on devices, normally-off are more complex (pdoping, Si-GaN cascode,...) have limited input dynamic range due to Schottky gate (except MISFET) 37

38 GaN Driver Integration: Motivation shoot-through currents conventional hybrid assembly V GS over-shoot & oscillations t Robustness: normally-off default behaviour Switching Speed: reduction of gate loop inductance Quasi normally-off GaN driver (Monolithic) Integration of Gate driver & power transistor 38

39 Normally-On GaN-on-Si HFET Quasi-Normally-Off GaN-on-Si HFET Mönch et.al. ISPSD 2015 V GS = 0V I D V DS I D V V GS 39

40 Boost Converter switching node Mönch et.al. ISPSD 2015 V IN V OUT GaN gate driver GaN 600 V HFET V G++ V G- No shoot-through currents robust Default: pull-down power transistor off Monolithic integration Hybrid integration 40

41 Hybrid GaN Power Module Mönch et.al. ISPSD 2015 Q1: GaN Power HEMT 100 mm, 24 A, 600 V D: GaN Schottky diode 50 mm, 12 A, 600 V Q PD : GaN HEMT 10 mm, 2.4 A, 600 V Q PU : GaN HEMT 10 mm, 2.4 A, 600 V 4x GaN diode, <100V, 10 mm 41

42 Turn-On and Turn-Off Transitions Turn-on t f,ds > 1.6 ns dv/dt MAX 91 V /ns t r,gs 5.4 ns no overshoot no oscillation fast switching Turn-off t r,ds > 1.2 ns dv/dt MAX 177 V /ns t f,gs 3.8 ns fast switching Mönch et.al. ISPSD

43 Monolithic Integration: Gate Driver & Power Transistor Parasitic gate loop inductance almost eliminated Monolithic combination of transistors with different voltage ratings Power transistor 600 V / 24 A Pull-up driver <100 V / 2.4 A Pull-down driver <100V / -1.2 A 3 x 2 mm 2 43

44 CONCLUSION 44

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46 Thank you for your attention Ingmar Kallfass University of Stuttgart Institute of Robust Power Semiconductor Systems Pfaffenwaldring 47 D Stuttgart Tel.: +49 (0) Fax: +49 (0) ingmar.kallfass@ilh.uni-stuttgart.de ILH is a member of ILH was founded in the frame of 46

47 References [Catrene] Integrated power & energy efficiency, Power device technologies, simulations, assembly and circuit topographies enabling high energy efficiency applications, Catrene Scientific Committee Working Group Integrated power & energy efficiency, Comm.pdf [BIS] UK Department for Business Innovation and Skills, Power electronics: A strategy for success, [ECPE] [Online] 47

48 Question and Answer Session Resources Power Electronics Applications Page keysight.com/find/power-electronics includes our Quick Start guide: Video clip: How to design DC-DC convertors keysight.com/find/eesof-how-to-dc-dc 48