Simulation of N-type MOSFETs and Tunneling Field-Effect Transistors

Transcription

1 Simulation of N-type MOSFETs and Tunneling Field-Effect Transistors by Zhixin Alice Ye Supervisor: Sorin Voinigescu April 2015

2 Abstract Simulation of N-type MOSFETs and Tunneling Field-Effect Transistors Zhixin Alice Ye B.ASc. in Engineering Science, Electrical and Computer Option Division of Engineering Science University of Toronto April 2015 Physical device-level simulations were conducted on next-generation n-type metal-oxide-semiconductor field-effect transistors (MOSFET) and tunneling field-effect transistors (TFET). A 2D, double-gated model of an n-type MOSFET was created and the DC and AC performance was investigated for channel lengths from 28 nm to 2 nm. Scaling results demonstrated improved high frequency characteristics with a tradeoff of increased leakage power. To address the issue of leakage power, TFETs were investigated as an alternative electronic device structure. A 2D InGaAs-AlGaAs heterostructure TFET was developed and characterized for DC performance. The TFET performance did not indicate improved subthreshold slope, indicating further refinement of doping profiles and bandgap structure may be required. ii

3 Acknowledgements This work would not have be complete without the help of a number of very smart and passionate people in the Voinigescu group. Of course, I am extremely grateful to Professor Sorin Voinigescu for his guidance, prompt feedback, and for keeping me on track throughout this project. To James Bateman, for his endless patience, stream of suggestions and tips, and helpful advice. Yuxi Liu, for sharing his progress with me as we both worked on our respective thesis projects. Jaro and Tim for troubleshooting my computer problems. The rest of the lab, for dealing with me and my silliness in good humour. And last but not least, all my friends and family for their continued support. Thank you. iii

4 Contents 1 Introduction 1 2 Background and Theory Modern Semiconductor Devices Transistor Figures of Merit Metal-Oxide-Semiconductor Transistor Scaling Threshold voltage roll-off in the linear region Drain-induced barrier lowering Bulk punch-through Tunneling Field-Effect Transistor Theory Semiconducting Materials and Heterostructure Properties Doping Implantation Literature Review Alternative Semiconductor Devices Tunneling Field Effect Transistors Material Selection Device Structure Band to Band Tunneling Model Zener Tunneling Schenk Model Hurkx Model Tunneling Field-Effect Transistor Design Considerations Summary and Remarks iv

5 4 Methods Research Objectives and Methodology Simulator Setup Determining Device Size and Parameters Experimental Outline Results and Discussion Initial NMOS Structure Scaled NMOS Structure N-type MOS Device Structure Effect of Scaling Extension to 3D-Nanowire Structure Tunneling Field-Effect Transistor Band Gap Diagram DC Characteristics Conclusion Summary of Results Future Work Bibliography 36 Appendices 38 A NMOS Scaling: SDE Deck 39 B NMOS Scaling: Sentaurus Device Deck 43 C 3D Nanowire: SDE Deck 47 D 2D TFET: Sentaurus Device Deck 51 v

6 List of Tables 2.1 Common figures of merit (FOM) used in transistor design and their descriptions Material Properties of Common Semiconductor Materials from [18], [16], and [13] Dimensions and parameters of scaled n-type MOSFET devices vi

7 List of Figures 2.1 Intel s 22nm FinFET Transistors Energy band diagrams showing the semiconductor from source to drain for the ON (solid line) and OFF (dashed line) of A. a long-channel NMOS device, and B. a short-channel NMOS device showing the DIBL effect [16] Punchthrough is shown when increasing the drain voltage increases the drain leakage current for Vg = -0.6 V. The dependence of current on Vd and shift in threshold voltage indicate short-channel effects. [16] A. Zener tunneling in a p-n junction, and B. Triangular potential barrier seen by tunneling electrons [15] Energy band diagrams for an n-type TFET for A. 0.1 Bias Zener Tunneling, B. Depletion Mode Device in OFF State, and C. Depletion Mode Device in ON State [15] Energy band diagram of A. two isolated semiconductors of different materials. B. An ideal p-n heterojunction at thermal equilibrium [16] Various n-type TFET structures. A. a single-gate lateral TFET; B. A double-gated vertical TFET; C. A single-gate lateral TFET with a n+ pocket under the gate; D. A double-gated lateral TFET with an n+ pocket under the gate [15] A. Schematic of a gate-all-around architecture of an InAs-Si heterostructure nanowire TFET. B. A scanning electron micrograph showing a cross-section of the TFET [8] Band-to-band tunneling current for a reverse-biased pn junction comparing a heterojunction performance vs a homojunction. The heterojunction shows higher tunneling current Degenerately doped semiconductors may begin tunneling prematurely, thus causing current to flow through the device before it is fully turned on Initial 14nm device structure, axes plotted on X-axis and Y-axis, scale in micrometers.. 22 vii

8 5.2 Transfer Characteristics of NMOS device for Vds = 0.05 V, 0.1 V, and 1.0 V. Gate Voltage in [V]. Drain current in [A/um] Output Characteristics of NMOS device for Vgs = 0.5 V, 1 V, and 1.05 V. Drain Voltage in [V]. Drain current in [A/um] Transconductance plot of NMOS device at varying voltages Scaled n-type MOSFETs from 28 nm to 2 nm. The colouring represents doping profile and concentration, with red indicating n-type doping and dark blue indicating p-type doping Comparison of Transfer Characteristics: Drain Current vs Gate Voltage for NMOS Device Scaling from 28nm to 2nm Comparison of Output Characteristics: Drain Current vs Drain Voltage for NMOS Devices Scaling from 28nm to 2nm Comparison of Transconductance: gm vs Voltage and gm vs Drain Current for NMOS Devices Scaling from 28nm to 2nm Comparison of Cutoff Frequency: Ft (Unit Gain Method) vs Gate Voltage for NMOS Devices Scaling from 28nm to 2nm Comparison of Cutoff Frequency: Ft vs Drain Current for NMOS Devices Scaling from 28nm to 2nm D NMOS reference design using all-around gate silicon nanowire structure Device structure for tunneling Field-Effect Transistor. Colours represent the doping concentration, and contacts are from right to left: source, gate, drain Lengthwise energy band diagrams for the initial TFET design in the OFF and ON state Transfer characteristics at two drain voltage bias points of the initial TFET structure. The gate voltage was simulated to 0.5 V and 1 V, respectively Output characteristics at two drain voltage bias points of the initial TFET structure. The gate voltage was simulated to 0.5 V for the green curve and 1 V for the red curve, respectively viii

9 Chapter 1 Introduction Historically, growth in the semiconductor industry has been driven by Moore s Law, which states that the size of a transistor must shrink by approximately 50% every two years. Traditionally this has resulted in improved device speed and reduced power; however the benefits of reducing the gate length of complementary metal-oxide-semiconductor (CMOS) devices below 14 nm are hampered by increased leakage current and reduced supply voltage scaling [8]. As meeting the predictions of Moores Law becomes more difficult, researchers have turned to various other possible device structures that may prove to be more power efficient and have improved I-V characteristics. One such novel device is the tunneling field effect transistor (TFET), which promises a number of advantages for low power applications: extremely low leakage current, and steep subthreshold slope below the 60mV/dec thermionic limit [4]. In addition, TFETs can be fabricated using the same fabrication techniques used for state-of-the-art silicon CMOS technology [10]. The TFETs extremely low OFF currents and low operating voltages could potentially facilitate low-power circuit designs and chips, and provide significant benefit in the field of electronic nanodevices. The TFET principle of operation differs from that of traditional CMOS field effect transistors by using the Zener tunneling mechanism as opposed to thermionic emission to transport carriers. Using this mechanism, the on current, I on, of the device is dependent on the transmission probability, T WKB, which can be estimated using the Wentzel-Kramer-Brillouin (WKB) approximation as: T W KB exp( 4λ 2m (E g ) 3 )[8] (1.1) 3q h(e g + φ) The screening tunneling length, λ, thus is related to the on current, and can be controlled by varying the gate voltage V g of the device. 1

10 Chapter 1. Introduction 2 The main goal of this project is twofold: first to characterize, using device simulation, the extreme scaling properties of an NMOS device from 28 nm to 2 nm, and simulate the DC and AC characteristics of the device. It is expected that the device will perform with improved high frequency characteristics at lower gate lengths, though this may come with a tradeoff of increased subthreshold slope and consequently greater power consumption. To address the issue of leakage power in MOSFET devices, the TFET explored as a potential alternative. The behaviour of a two-dimensional TFET device with gate length comparable to that of MOSFETs in the next technology node (14 nm) will be investigated to evaluate whether this device could prove superior to traditional CMOS technology in terms of performance and power consumption. The hypothesis is that the tunnel FET will have significantly steeper subthreshold slope and reduced leakage current, but with a trade-off of lower ON currents and reduced efficiency for high speed switching applications. Heterojunction materials will be selected to optimize the TFET structure and performance. If time allows, the TFET performance can also be optimized by adjusting the structure, materials, doping profile, and scaling. Though the n-type MOSFET remains an important device at small scales, TFETs prove promising for low-power applications because they are the only ones that can have steeper subthreshold slope as needed to reduce the supply voltage in ICs. The TFETs extremely low OFF currents and low operating voltages could potentially facilitate low-power circuit designs and chips, and provide significant benefit in the field of electronic nanodevices.

11 Chapter 2 Background and Theory 2.1 Modern Semiconductor Devices Among the major players in the semiconductor industry such as Intel and TSMC, Moore s Law has continued for the past few years despite poor planar MOSFET performance. This has been achieved through the implementation of a variety of innovations including incorporating strain into the channel, using a high-k dielectric, and using a three-dimensional transistor structure such as a trigate or finfet structure. These changes allow these companies to improve performance by incorporating incremental improvements in fabrication methodology. However, the International Technology Roadmap for Semiconductors predicts that CMOS devices will still reach fundamental limits in scaling around 2018 that must be overcome [2]. (a) 3D model of Intel s 22nm (b) SEM of Intel s physically implemented trigate technology. Conducting 22 nm trigate struc- channels are formed on three sides tures. Finning is completed by of a vertical fin structure, providing fully depleted operation. connecting multiple drains and sources under a single gate [9]. Figure 2.1: Intel s 22nm FinFET Transistors 3

12 Chapter 2. Background and Theory Transistor Figures of Merit Table 2.1: Common figures of merit (FOM) used in transistor design and their descriptions Figure of Merit Symbol Definition On Current, or I on The current at the drain when the device is in saturation I D,Sat mode. Off Current, or I off The current at the drain when the device is in cutoff mode. I D,Cutoff Threshold Voltage V T The minimum gate-to-source voltage needed to create conduction between the source and drain of the device. Subthreshold Slope SS Specific to MOSFETs, the SS describes the slope of the logarithmic plot of drain current vs. gate voltage in the region below the threshold. This provides an indication of the power lost during device switching. RF/High Speed Analog Design Transconductance g m Fre- Cutoff quency Maximum Oscillation Frequency F T F max Transconductance describes how output current varies with respect to input voltage, with g m = I out / V in The cutoff frequency is defined as the frequency where the current gain drops to 0dB, and can be defined as: 2πF T = g m /C gs where C gs is the gate-to-source capacitance. The maximum oscillation frequency describes the frequency when power gain drops to 0dB. Power Design Figure of Merit r ds(on) Q g A quick measure for power performance and efficiency, the FOM takes into account both conduction losses and switching losses in a power MOSFET design [6]. Here, Q g is the quality factor of the system, or the ratio of power stored to power dissipated. Digital Design Gate Delay τ gate The length of time for a signal (switch from on-off or off-on) to propagate through a device. To provide an objective perspective and evaluation of electronic devices, Figures of Merit (FOM) are commonly used metrics that describe device performance. Transistor performance parameters vary depending on the purpose of the device, and other considerations such as size and cost of production should also be included. For digital logic applications, the main considerations are a high on-off current ratio (I on /I off ) and subthreshold slope to minimize switching power losses. Other metrics for RF and Power applications are described in Table 2.1. Different transistors can be optimized for various purposes and combined in a single circuit during the processing of a single System-on-Chip (SOC).

13 Chapter 2. Background and Theory Metal-Oxide-Semiconductor Transistor Scaling Scaling down the MOSFET is a continuous trend known as Moore s Law. Smaller devices improve the driving current, I D, therefore also improving operation performance and reducing area [16]. However, for very small devices, the performance begins to deviate from so-called long-channel devices due to short channel effects including [16]: Threshold voltage roll-off in the linear region Drain-induced barrier lowering (DIBL) Bulk punch-through Threshold voltage roll-off in the linear region When the source and drain depletion regions become a significant portion of channel length, it is possible that the voltage applied across the drain and source of an NMOS device can modulate the threshold voltage of the device instead of staying roughly constant. This can be modeled by the following equation: V T = qn AW m r j ( C o L 1 + 2W m r j 1) (2.1) where W m is the depletion width, r j is the junction depth, L is the channel length, and C o is the gate oxide capacitance. Thus at larger drain voltages the voltage at the gate required to turn on the device is decreased for an n-type MOSFET Drain-induced barrier lowering Drain-induced barrier lowering occurs when the drain is located close to the source, and the drain bias can influence the energy barrier height at the source end. This can cause an increase of current for short-channel devices, and again the threshold voltage would be expected to decrease with increasing drain bias [16].

14 Chapter 2. Background and Theory 6 Figure 2.2: Energy band diagrams showing the semiconductor from source to drain for the ON (solid line) and OFF (dashed line) of A. a long-channel NMOS device, and B. a short-channel NMOS device showing the DIBL effect [16] Bulk punch-through For a sufficiently large drain voltage, significant leakage current may begin to flow from drain to source from the bulk of the substrate, and the depletion-layer width of the drain can also increase with increased drain voltage. Figure 2.3: Punchthrough is shown when increasing the drain voltage increases the drain leakage current for Vg = -0.6 V. The dependence of current on Vd and shift in threshold voltage indicate short-channel effects. [16].

15 Chapter 2. Background and Theory Tunneling Field-Effect Transistor Theory Figure 2.4: A. Zener tunneling in a p-n junction, and B. Triangular potential barrier seen by tunneling electrons [15]. The TFET principle of operation differs from that of traditional CMOS field effect transistors by using the Zener (aka band-to-band) tunneling mechanism as opposed to thermionic injection as the primary mechanism of transporting charge carriers. In the simplest case, a quantum tunneling treatment can be used to solve for a finite well potential (picture of quantum well tunneling). For a tunneling field-effect transistor, the potential barrier across the gate can be approximated as a triangular potential, as shown in figure 2.4. The expression for a particle tunneling through this potential barrier can be found by solving Schrodingers equation for a triangular barrier, and the time-dependent Schrodingers equation is equal to: i h d ( ) h 2 Ψ(r, t) = [ dt 2µ 2 + V (r, t)]ψ(r, t) (2.2) Here is the particles reduced mass, V is the potential energy, 2 is the Laplacian, and Ψ is the wavefunction. Solving this expression for Ψ will provide enough information to approximate the probability of tunneling current flowing through the device, leading to a band-to-band tunneling current that drives the tunneling FET design. In the case of the triangular tunneling barrier shown in Figure 2, V(r,t) is

16 Chapter 2. Background and Theory 8 defined as: qxξ + E g, if 0 < x < d V (r, t) = 0, otherwise (2.3) The general solution for Schrodingers equation in one dimension is then: A 1 e ik0x + A 2 e ik0x if x 0 Ψ(x) = B 1 e ik1x + B 2 e ik1x if 0 < x < d (2.4) C 1 e ik2x + C 2 e ik2x if x d The full solutions can be found by solving with boundary conditions. However, we realize that the functions wave number, k, is defined as: k(x) = 2m g h 2 (E x V (x)) (2.5) Using the Wentzel-Kramer-Brillouin (WKB) approximation, below, the tunneling probability can then be approximated: T W KB exp 2 d 0 k(x) dx (2.6) This transmission probability describes how likely it is for a particle to tunnel through the potential barrier of the device, and must be between 0 and 1. The final tunneling probability can then be calculated for the triangular potential well: T W KB exp 4 2m ge 3 2 g 3q hξ exp E Ē (2.7) Here, Ē = qhξ 2 2m g Eg is a factor that determines the impact of the transverse-energy-state carriers on the tunneling magnitude [15]. By varying the gate voltage, VG, of the device, it is possible to tune the tunneling probability, which contributes to the current flowing through the device. Finally, the Zener tunneling current density is calculated by integrating charge flux tunneling probability from the p+ side to the n+ side: J = qv g (k)ρ(k)ρ (k )dk2π k dk (f v f c )T W KB (2.8) The tunneling probability therefore depends on the size of the bandgap as well as the effective mass of the device. The energy band diagrams for an ntfet depletion-mode device looks as follows:

17 Chapter 2. Background and Theory 9 Figure 2.5: Energy band diagrams for an n-type TFET for A. 0.1 Bias Zener Tunneling, B. Depletion Mode Device in OFF State, and C. Depletion Mode Device in ON State [15]. The bandgap size can be modulated by applying a voltage across the gate of the TFET, and the effective mass can be controlled using the relationship: m = 1 d 2 E dk 2 (2.9) Changing the effective mass would therefore involve making modifications in the material structure of the TFET device (eg. doping, different substrate materials), while changing the size of the bandgap can be tuned by biasing the gate voltage of the TFET. In contrast to MOSFETs, tunneling FETs are ambipolar for the above device, it would show p-type behaviour for dominant hole conduction and n-type behaviour for dominant electron conduction. To compensate for this, it is possible to design an asymmetric doping profile (heavier hole-dominant doping) or using heterostructures to restrict the movement of one type of charge carrier [8]. This asymmetry also produces the major advantage of TFETs: a low leakage (off-state) current. When the TFET is in the off state, the tunneling barrier is very high, so holes and electrons are extremely unlikely to tunnel through a barrier. However, modulating the applied gate voltage of the device will lower the barrier of the device, forcing it into an ON state with a passable barrier for current to flow.

18 Chapter 2. Background and Theory Semiconducting Materials and Heterostructure Properties Semiconductor materials are nominally small band gap insulators. Silicon is by far the most common material still because of its maturity in the market, its well-defined manufacturing processes for largescale integrated circuits, as well as its abundance of supply. Other common compound semiconductors used in electronics include GaAs and SiGe. For device design, engineering the bandgaps between different parts of a device can often lead to improved performance. This can be done by implementing a heterostructure junction in some devices, where different materials are used in the different parts of the device based on the desired bandgap[16]. III-V materials, containing a compound of materials from Group III and Group V of the Periodic Table of Elements, are very popular for this case. III-V materials allow the ability to tune the bandgap of the material based on the proportions of the III-V materials contained in each compound. A chart comparing a representative sample of relevant material properties is supplied below. In particular, the Al x Ga 1 x As and In x Ga 1 x As families were investigated for this project. Table 2.2: Material Properties of Common Semiconductor Materials from [18], [16], and [13] Electron Affinity m lh /m 0 m e /m 0 Lattice Constant Si 4.05 ev Angstroms Ge 4.0 ev Angstroms Al 0 Ga 1 As 1.42eV Angstroms at 300K Al 1 Ga 0 As 2.17eV N/A N/A Angstroms at 300K Al 0.5 Ga ev As 0.3 Sb 0.7 Angstroms In 0.8 Ga 0.2 As 4.73 ev Angstroms at 300K In 0.53 Ga 0.47 As 0.75 ev Angstroms at 295K Eg (ev) Electron Mobility (µ) ev 1360 cm 2 V 1 s ev 3900 cm 2 V 1 s 1 N/A N/A N/A N/A 1.36 N/A 0.50 N/A ,000 cm 2 V 1 s 1 These parameters are important to the performance of the semiconductor to align the bandgap of the respective materials at a junction. As shown in the figure below, bandgap alignment is dependent on both the electron affinity and the size of the bandgap of the material. The material lattice constants must also be considered to include the effects of lattice strain at a heterojunction. For the purposes of

19 Chapter 2. Background and Theory 11 this project, strain was not investigated, so lattice-matched materials were picked and only the bandgap modified. Figure 2.6: Energy band diagram of A. two isolated semiconductors of different materials. B. An ideal p-n heterojunction at thermal equilibrium [16].

20 Chapter 2. Background and Theory Doping Implantation The defining property of a semiconductor material is that it can be doped with impurities that alter its electronic properties in a controllable way, by shifting the location of the bandgaps with respect to the Fermi energy levels of a device. The Maxwell Boltzmann approximation is typically used, and is applicable for non-degenerate semiconductors in the limit of high temperature and low particle density, or when the following condition is satisfied: e (εmin µ)/kt 1 (2.10) Here, ε min is the lowest (minimum) value of ε i. as: In this case, the approximation that is used to estimate the Fermi energy level can be approximated n = n i exp E f E i [16] (2.11) kt p = n i exp E i E f [16] (2.12) kt For very highly doped semiconductors less than 3kT above E v or less than 3kT below E c, the Maxwell-Boltzmann approximations no longer apply and there is no easy analytical solution for the electron materials. Instead, the Fermi-Dirac equations must be solved analytically. n = Etop 0 N(E)F (E)dE (2.13) where N(E) is the density of states, and F(E) is the Fermi-Dirac equation as outlined below: F (E) = e (E E F )/kt (2.14)

21 Chapter 3 Literature Review 3.1 Alternative Semiconductor Devices Various structures and devices have been proposed as potential future devices beyond CMOS. The single-electron transistor (SET) has been proposed as a potential logic element device that is small in size and has low power consumption. This device consists of two tunnel junctions that share a common electrode, thus the electrons may only use tunneling as a mechanism to transport electric current [11]. Carbon nanotube field-effect transistors (CNFETs) have also been suggested as a device that utilizes the high conductivity of 2-dimensional carbon to transmit electrons. Though graphene is inherently conducting, modifying the chirality of carbon nanotubes can control the material to behave like a semiconductor [19]. Junctionless nanowire field-effect transistors (JNTs) have also been considered as an alternative that provides a nearly ideal subthreshold slope and good on-state current [6]. On a grander scale, it is also possible to develop devices that use state variables other than solely electric charge to transfer information, for example, electron spin, phase, and molecular states [2]. Tunneling field-effect transistors are a promising alternative because of their ability to have a steep threshold voltage below the fundamental limit of 60 mv/dec for MOSFETs and BJTs [15]. This reduces power consumption because supply voltages can consequently be scaled to less than 0.5 V. Another key advantage to TFETs is their low source-drain leakage, which poses significant advantages in reducing current when transistors are in the off state. These potential advantages would theoretically allow TFETs to achieve lower standby power and also allow less power to be lost during the switching of the circuit compared to traditional MOSFET devices. In todays mobile-centric world, power represents an increasing concern in circuits and tunneling field-effect transistors provide an opportunity to reduce power consumption by up to

22 Chapter 3. Literature Review 14 times on a fundamental level [8]. 3.2 Tunneling Field Effect Transistors A number of different designs for TFETs have been proposed in literature, which differ in bandgap selection, oxide/dielectric selection, device structure, and other design parameters. Below I have attempted to overview a few possibilities to illustrate the breadth of options Material Selection Various materials have been utilized in the gate, source, and dielectric of electronic devices. Examples of recent improvements to devices include the use of III-V heterojunction materials such as GaAs, as well as SiGe. High-K dielectrics with metal gates are now also often used to reduce the thickness of the gate dielectric [19]. Asbeck et. Al describe a TFET developed using III-V based tunnel heterojunctions that may operate as low as 0.3 V, with an Ion/Ioff ratio of 8. The proposed TFET allows for a good balance between power consumption and performance, however, the III-V semiconductor design may prove more difficult to fabricate compared to traditional CMOS processes due to the use of more exotic material combinations, such as InAlAs and InGaAs [18]. 2-dimensional materials have also been suggested as a possible method of reducing the dimensions of the device. The high conductivity of 2-dimensional carbon has been attractive for its higher current throughput, though currently manufacturability of graphene devices has proved challenging [5]. Lundstrom et. al discuss simulations that were undertaken to explore how carbon nanotubes be optimized for TFET performance [12]. However, one issue with carbon nanotubes is their fabrication difficulty, as it is difficult to accurately grow carbon nanotubes in a regular pattern. Furthermore, simulations do not account for the real performance of the material, as defects in the nanotube structure could dramatically decrease current throughput Device Structure A number of different designs for tunnel FETs have been proposed in literature that range in feasibility, change from previous designs, and performance. Traditional single-gated structures are simple to manufacture, however, TFET designs using a planar TFET do not appear to have appreciable on-current characteristics above A/m [3]. Double-gate tunnel FETs are another possibility that provides more current than their single-gate counterparts, with an Ion/Ioff ratio of more than and on current up to 0.23mA [1]. The design mentioned in this paper, however, does not investigate the scaling impact of

23 Chapter 3. Literature Review 15 TFETs, since the design was built at a 50nm gate length. Other structures that have been developed incorporate modified doping profiles and vertical finfet structures, as shown in the figure below: Figure 3.1: Various n-type TFET structures. A. a single-gate lateral TFET; B. A double-gated vertical TFET; C. A single-gate lateral TFET with a n+ pocket under the gate; D. A double-gated lateral TFET with an n+ pocket under the gate [15]. Other novel structures that have been explored include those that further increase the gate surface area, for example a gate-all-around architecture, which can be seen in a silicon nanowire FET [8]. These structures have been combined with an InAs-Si heterostructure and prove promising in reducing device area. Figure 3.2: A. Schematic of a gate-all-around architecture of an InAs-Si heterostructure nanowire TFET. B. A scanning electron micrograph showing a cross-section of the TFET [8].

24 Chapter 3. Literature Review Band to Band Tunneling Model The original Band to Band Tunneling Model discussed in use during the tunneling transistor simulations in this thesis project make use of the Zener tunneling mechanism. The follow subsections will discuss briefly the Zener model, as well as some of the updated models used during the course of this experiment Zener Tunneling Zener tunneling is considered a form of dielectric breakdown, which occurs when the number of electrons in an unfilled band suddenly increses as the field strength passses a critical value. Using the Bloch model, it is possible to calculate the rate at which electrons escape from the lower into the upper energy bands via Zener tunneling, with the main result for a one-potential barrier being [20]: γ = ef a h exp ( π2 maɛ 2 h 2 ef ) (3.1) where γ represents the rate at which an electron can pass from one region to another side of the potential barrier into the conduction band of a dielectric. To actually implement the Zener tunneling model in simulation, however, requires some more modern simulation models described below Schenk Model The Schenk Model proposes that band-to-band tunneling under conditions set by Zener do not reach the same currents observed in experimental results. This indicates that some mechanism such as phononassisted band-to-band tunneling occurs in steep p-n junctions (with doping greater than 1 10e19 cm 19 ), or in high normal electric fields. Green s function formalism is used to analyze electron-phonon collisions that propagate electrons that initially tunnel via band-to-band tunneling [14] Hurkx Model The Hurkx model for band-to-band tunneling is modelled by an additional generation-recombination process, therefore including both trap-assisted tunneling as well as band-to-band tunneling [7]. Trap assisted tunneling is an important point to consider, as impurities in semiconductor devices will allow electrons to tunnel through a junction even if the valence band is not located below the conduction band of the other portion of the junction. For the purposes of the simulations conducted through this project, the Hurkx model was used due to its ability to converge on a solution as well as its increased accuracy over simple Zener band-to-band tunneling.

25 Chapter 3. Literature Review Tunneling Field-Effect Transistor Design Considerations A number of key aspects are considered when choosing the materials, structure, and doping profile of a tunnel-fet design. Based on reference designs, III-V semiconductor systems seem to provide superior performance [18]. In particular, the InGaAs/AlGaAsSb system appears promising because of a wide range of band lineup configurations that can be provided, the ability to vary band lineup over a wide energy range by tuning material composition, as well as easy lattice matching due to the tunability of the system. By choosing different proportions of group III and group V materials, properties can be engineered to desired bandgaps. Another consideration is the use of a staggered heterojunction as opposed to a homojunction of uniform material in the source, drain, and channel. Figure 3.3: Band-to-band tunneling current for a reverse-biased pn junction comparing a heterojunction performance vs a homojunction. The heterojunction shows higher tunneling current. [18] Staggering materials in a heterojunction, though much more difficult to fabricate, offers up to a 100x enhancement in tunneling current, as shown in figure 3.3.

26 Chapter 3. Literature Review 18 Figure 3.4: Degenerately doped semiconductors may begin tunneling prematurely, thus causing current to flow through the device before it is fully turned on. [17] Lastly, the doping profile to achieve a steep subthreshold slope is important. For MOSFETs, source regions are usually heavily doped, however, for TFETs this may not be ideal due to the tail of electrons that lie above the Fermi energy. These electrons may be able to tunnel through a TFET prior to the device being fully switched on, resulting in a more shallow slope as shown in Figure 3.4. It is recommended to reduce source doping somewhat to mitigate this effect. 3.5 Summary and Remarks Overall, though numerous designs of tunneling field-effect transistors have been proposed, these devices have not reached the same level of scaling and performance that would enable future electronic TFETs to be fully functional and available to build on current silicon fabrication technology. Further research can be conducted to investigate the impact of scaling to the 10 nm node. It is yet unclear whether or not the ON current of the device will be sufficient to drive current, so enabling a high on current is desirable.

27 Chapter 4 Methods 4.1 Research Objectives and Methodology For the purpose of this project, a 2 dimensional double-gate NMOS structure was first implemented in Sentaurus to understand the impact of structure on device physics and properties. A double-gated structure was chosen to increase the ON current of the device compared to single-gated structures [1], and a two-dimensional structure was chosen to reduce simulation time. The DC transfer characteristics and output characteristics were plotted to verify functionality. A silicon wire 3D model was also developed, demonstrating feasibility of 3D simulations for a nanowire or gate-all-around structure. For the purposes of this thesis, the 2D structure was used to reduce simulation time. Scaling was investigated on the device by simulating a series of similar n-type MOSFETs with gate lengths ranging from 28nm to 2nm and scaling other parameters appropriately. Parameters including ft vs. Id, ft. vs. Vds, gm vs Id, and gm vs. Vds were simulated to gather figures of merit for the device. The high frequency characteristics of the devices were expected to improve as gate length scaled down, while other aspects such as leakage current were expected to degrade depending on gate length. Following this study on scaling, another intermediate structure using InGaAs in the channel instead of silicon was developed so as to understand how the different material would impact the performance of the n-type MOSFET. The simulations of this material was compared to the performance of a siliconbased device to ensure that the impact of switching to a III-V compound would not greatly impact device performance. Then, the doping profile of the InGaAs device was modified to match that of a TFET, and a 2- dimensional TFET heterostructure was developed using InGaAs and AlGaAs. III-V compounds were 19

28 Chapter 4. Methods 20 used for the TFET to ensure better performance through improving the bandgap structure [18]. Some iterations and optimization were required in this process to understand the effect of varying the doping profiles, the structure size, as well as the material composition. The bandgap structure of the device as well as preliminary transfer characteristics that show tunneling behaviour are included to demonstrate basic functionaly of the TFET. 4.2 Simulator Setup In order to model the behaviour of a semiconductor device, software packages exist to conduct simulations with various levels of physics integrity, ranging from compact SPICE models for small-scale integrated circuits to individual atomic-scale physics-driven simulators such as Atomistix. Ideally the device simulator should capture the tunneling behaviour of TFETs as well as provide accurate simulations of DC, small signal, and large-signal operation of the device. A number of simulation tools are available at the desired level for this project, including quantum effects and band energy-diagram-driven diagrams. Synopsys offers a device modeling package called Sentaurus Device, which offers the ability to define a device structure from both process simulation steps (SPROCESS) and through manually defined structures (using Sentaurus Structure Editor). These packages were readily available within the university software and thus did not require additional funds to acquire. In addition, a number of prior TCAD models and sample libraries are readily available on Sentaurus to provide examples on how to set up projects, therefore it was the most accessible choice for this project. In addition, it is possible to enable all necessary physics models in the software, from classical electronic models to Fermi-Dirac electronic equations and quantum tunneling effects. 4.3 Determining Device Size and Parameters A number of different approaches could be taken in defining the device structure. Either a more complex 3D model could be used, or a simpler model that would be easy to build and understand the device physics. For simplicity s sake, an initial 2D model was developed in silicon that consisted of a 10nm long gate with a lateral doping profile, of 4 nm in thickness. A 10nm-long double gate was implemented to increase the on current of the device, which has been shown to improve performance over a single-gated device [1]. A 2nm thick high-k dielectric of HfO 2 was used for the dielectric, with 20 nm spacers initially placed on either side of the gate. No contact resistance was modelled. The doping profile for the NMOS

29 Chapter 4. Methods 21 device consisted of a atoms/cm 3 arsenic concentration. The channel region was lightly doped with atoms/cm 3 of boron. When scaling the device to smaller gate lengths, the device was scaled such that the source, channel, drain, and oxide lengths all remained proportional in length. Compared to the initial device, the doping profile was made much more abrupt. The oxide material was varied as well: for the 28 nm device SiO 2 was used, and Si 3 N 4 was used for the 20nm and 14nm devices. Below 14nm, all devices had a high-k dielectric, HfO 2. For the tunneling field-effect transistor a device was implemented with the original gate length set to 20nm. The device had a channel and drain of InGaAs and a source of AlGaAs. InGaAs was selected for the channel and drain for its high electron mobility properties greater than 10,000 cm 2 V 1 s 1. To ensure a proper heterojunction between the channel and source, AlGaAs was used as a material with similar lattice parameters and a valence band level that matched the valence band edge of InGaAs. A representative Sentaurus Device Editor (SDE) deck is provided in Appendix A. The AC/DC device simulation deck can be found in Appendix B. 4.4 Experimental Outline The experiments and major results obtained from each device structure included the following: Initial n-type MOSFET: Transfer characteristics, output characteristics, and transconductance information was gathered at 3 bias points. It was found the initial length of the spacers was somewhat limiting, so the size of the spacer and source/drain also impacted the results. The next iteration of the device thus reduced the size of the spacer. Scaled n-type MOSFET: The devices were characterized for both their DC characteristics (transfer characteristics and output characteristics) as well as their AC characteristics (Cutoff frequency and transconductance), which were plotted both against Vg and Id. InGaAs TFET: A preliminary transfer plot and energy band diagrams were plotted to verify basic tunneling capability.

30 Chapter 5 Results and Discussion 5.1 Initial NMOS Structure The initial device structure had the following shape and doping profile. (a) Initial NMOS Device Structure with high-k gate dielectric and long spacer. (b) Device doping concentration, showing a gradient in transition from p-type to n-type doing region. Figure 5.1: Initial 14nm device structure, axes plotted on X-axis and Y-axis, scale in micrometers Initial trials were conducted to gather the DC transfer characteristics at Vds = 0.05 V, 0.1 V, and 1.0V, as well as the output characteristics at Vgs=0.5V, 1V, and 1.2 V from the NMOS reference design, and the resulting I-V curves are shown in Fig. 9 and 10 below. DC results from the transfer characteristics indicate a Id,lin of approximately 0.3 ma/um with SSlin of around 66 mv/dec, and Id,sat of around 1mA/um with an SSsat of about 67 mv/dec. These are roughly in agreement with current 22

31 Chapter 5. Results and Discussion 23 semiconductor technology. Figure 5.2: Transfer Characteristics of NMOS device for Vds = 0.05 V, 0.1 V, and 1.0 V. Gate Voltage in [V]. Drain current in [A/um]. Figure 5.3: Output Characteristics of NMOS device for Vgs = 0.5 V, 1 V, and 1.05 V. Drain Voltage in [V]. Drain current in [A/um]. The output characteristics indicate an increasing trend of greater drain-to-source current for pro-

32 Chapter 5. Results and Discussion 24 gressively higher gate voltage, as expected. The body was not biased for this device, explaining the difference in threshold voltages. Figure 5.4: Transconductance plot of NMOS device at varying voltages. These results show a measured gm,lin of 1.08mS/um at Vg = 0.52V and gm,sat of 1.7 ms/um at Vg = 0.64 V. Some explanation for the gm performance could be due to the large size of the spacers in the device, which could cause high source-to-drain resistance. The overall data gather so far verifies the NMOS model developed, and provides a control reference to compare with the tunneling FET performance. 5.2 Scaled NMOS Structure N-type MOS Device Structure The n-type MOSFET structure was refined with a more abrupt doping profile, and this device was then scaled to smaller sizes from 28nm to 2nm. The breakdown of device lengths and parameters is included in Table 5.1.

33 Chapter 5. Results and Discussion 25 Structure Name Gate Length (nm) Table 5.1: Dimensions and parameters of scaled n-type MOSFET devices A B C D E F G Tox (nm) Tchannel (nm) SiO2 Si3N4 Si3N4 HfO2 HfO2 HfO2 HfO2 Oxide Material Source length (nm) Source Material Silicon Silicon Silicon Silicon Silicon Silicon Silicon Drain Length (nm) DrainMaterial Silicon Silicon Silicon Silicon Silicon Silicon Silicon SpacerLength (nm) N source [cm3]-1 N drain [cm3]-1 N channel [cm3] E E E E E E E E E E E E E E E E E E E E E+15 GateBarrier Bias Point 1 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Bias Point 2 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vs = 0 Vd = 0.3V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vd = 0.6V Vg = 1.0V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Vg = 1.5V Ft frequency range 1e10-1e12 Hz 1e10-1e12 Hz 1e10-1e12 Hz 1e10-1e13 Hz 1e10-1e13 Hz 1e10-1e13 Hz 1e10-1e13 Hz

34 Chapter 5. Results and Discussion 26 (a) Lg = 28nm (b) Lg = 20nm (c) Lg = 14nm (d) Lg = 10nm (e) Lg = 7nm (f) Lg=5nm (g) Lg=2nm Figure 5.5: Scaled n-type MOSFETs from 28 nm to 2 nm. The colouring represents doping profile and concentration, with red indicating n-type doping and dark blue indicating p-type doping The resulting devices developed in Sentaurus Device Editor (SDE) are shown roughly to scale in Figure 5.5. The colours indicate the doping type and concentration along the device. As can be seen, the ratio between the source, channel, and drain, as well as the thickness of the channel and oxide thickness were kept to scale during the scaling. The dielectric permittivity of the gate oxide was also increased during the course of the scaling in order to demonstrate improved performance Effect of Scaling The DC Characteristics of the device are plotted below, as indicated. Firstly the transfer characteristics were plotted on a log scale with respect to gate voltage for two different drain bias points. The output characteristics were also plotted to find the relationship between drain voltage and drain current. (a) Transfer Characteristics, Vd biased to 0.3V (b) Transfer Characteristics, Vd biased to 0.6V Figure 5.6: Comparison of Transfer Characteristics: Drain Current vs Gate Voltage for NMOS Device Scaling from 28nm to 2nm

35 Chapter 5. Results and Discussion 27 (a) Output Characteristics, Vg biased to 1V (b) Output Characteristics, Vg biased to 1.5V Figure 5.7: Comparison of Output Characteristics: Drain Current vs Drain Voltage for NMOS Devices Scaling from 28nm to 2nm Based on Figure 5.6 and 5.7, it can be seen that the general trend in drain current is to increase with smaller-scaled transistors. For example, the ON current between Lg = 5nm and Lg = 2nm for figure 5.7a is shown to improve from around 5 ma/width to 7 ma/width. This is a signficant increase in performance by scaling to smaller gate lengths. The subthreshold slope of the devices was found to range between 65 mv/dec for the Lg=2nm device at Vd = 0.6V and 73 mv/dec for the Lg=28nm device at Vd = 0.3V. This indicates that subthreshold slope does not change significantly for relatively low drain bias voltages that were used in this study. Lastly, the off current (when Vg = 0 V) increased with smaller scales from 28nm to 20nm to 14nm, however the off current can significantly be reduced at smaller scales by using a high-k dielectric, which would reduce the gate-drain current significantly, as was used for small gate lengths.

36 Chapter 5. Results and Discussion 28 (a) Transconductance, Vd biased to 0.3V (b) Tranconductance, Vd biased to 0.6V (c) Transconductance vs Drain Current, Vd biased to 0.3V (d) Tranconductance vs Drain Current, Vd biased to 0.6V Figure 5.8: Comparison of Transconductance: gm vs Voltage and gm vs Drain Current for NMOS Devices Scaling from 28nm to 2nm As shown in Figure 5.8, the scaling of smaller gate lengths show signficant improvements in transconductance over a relatively smaller range of gate voltage for the extremely scaled (Lg = 2nm) devices. This is promising, though it remains to be further confirmed, since parasitics were not used in the device simulations.

37 Chapter 5. Results and Discussion 29 (a) Cutoff Frequency vs Vg, Vd biased to 0.3V (b) Cutoff Frequency vs Vg, Vd biased to 0.6V Figure 5.9: Comparison of Cutoff Frequency: Ft (Unit Gain Method) vs Gate Voltage for NMOS Devices Scaling from 28nm to 2nm (a) Cutoff Frequency vs Id, Vd biased to 0.3V (b) Cutoff Frequency vs Id, Vd biased to 0.6V Figure 5.10: Comparison of Cutoff Frequency: Ft vs Drain Current for NMOS Devices Scaling from 28nm to 2nm Based on figure 5.10, it is seen that in addition to the improved transconductance, the cutoff frequency of highly scaled devices is also improved. This indicates continued improvement of small devices in high power applications, with a potential cutoff frequency of over 4000GHz for the 2nm device.

38 Chapter 5. Results and Discussion Extension to 3D-Nanowire Structure To extend and further understand the performance of the device, a reference 3D model of a siliconnanowire device was developed in Sentaurus, with the full simulation device deck available in Appendix C. The device was developed to match the structure of the 2D device in dimensions and doping profile, and a mesh was defined in 3 dimensions. Simulations have not been conducted on this design yet due to time and computing power constraints, and will become part of the future work. (a) 3D view of silicon nanowire structure with gate oxide. (b) 3D side view of silicon nanowire without gate oxide to show doping profile Figure 5.11: 3D NMOS reference design using all-around gate silicon nanowire structure. 5.3 Tunneling Field-Effect Transistor Figure 5.12: Device structure for tunneling Field-Effect Transistor. Colours represent the doping concentration, and contacts are from right to left: source, gate, drain The design for the tunneling FET was done based off of the structure for the 2D NMOS device, with modifications made to develop a heterojunction device and changes made to the doping profile. A reference design for tunneling field-effect transistor based on a paper described by Wang et al [18] was