Ambipolar electronics

Transcription

1 Ambipolar electronics Xuebei Yang and Kartik Mohanram Department of Electrical and Computer Engineering, Rice University, Houston Rice University Technical Report TREE12 March 2, 21 Abstract Ambipolar conduction, characterized by a superposition of electron and hole currents, has been observed in many next-generation devices including carbon nanotube, graphene, silicon nanowire, and organic transistors. This paper describes exciting new design opportunities in both analog and digital domains, all of which are inspired by the ability to control ambipolarity during circuit operation. We illustrate this with (i) a single-transistor polarity controllable amplifier, which can greatly simplify communication circuits and (ii) polarity controllable ambipolar logic gates, which are highly expressive yet compact compared to conventional CMOS. 1 Motivation Ambipolar conduction, characterized by a superposition of electron and hole currents, has been experimentally reported in many post-silicon devices including carbon nanotubes [1] graphene [2], silicon nanowires [3, 4], organic single crystals [5], and organic semiconductor heterostructures [6]. As opposed to unipolar silicon CMOS devices whose p-type or n-type behavior is determined during fabrication, ambipolar devices can be switched from p-type to n-type by changing the gate bias, e.g., [4, 7]. Ambipolar conduction is illustrated by the I-V curves for graphenebased transistors in Figure 1, where high transconductance required for analog applications and high I on /I off required for digital applications are observed, respectively. Note that the drain current first decreases and then increases with increasing gate-source voltage, exhibiting p-type behavior with dominant hole conduction and n-type behavior with dominant electron conduction, respectively. As seen in the figure, a minimum conduction point V min exisits for all ambipolar devices. Since conventional analog and digital circuits are based on unipolar devices, this novel ambipolar behavior was initially considered undesirable and several techniques based on channel, gate, and contact engineering were explored to suppress the ambipolar behavior [8 1]. However, recent work has shown that the ability to control device polarity (p- or n-type) in-field presents new design opportunities in both analog and digital domains [11 14]. This position paper generalizes the design principles of ambipolar electronics, presents new designs and applications, and outlines challenges for the future. 2 Analog circuits In the analog domain, ambipolar conduction can be used to simultaneously achieve both positive and negative gain by controlling the gate bias. We illustrate this using a single transistor amplifier, called the output polarity controllable (OPC) amplifier. The OPC amplifier, whose schematic is shown in Fig. 2(a), is based on the common source/drain amplifier for unipolar devices. When an ambipolar transistor is used to replace the unipolar transistor, the choice of bias point(s) results in simple yet highly efficient designs for core analog components such as full-wave rectification, frequency doubling, phase shift keying, and phase detection. The first such design reported in literature, based on Yang and Mohanram: Rice University TREE12 1

2 x Figure 1: Ambipolar conduction in graphene-based transistors exibiting (a) high transconductance [15] and (b) high I on /I off [16] graphene, uses a single bias point such that V bias = V min [14]. In this configuration, the output of the OPC amplifier has a fundamental frequency that is double that of the input signal and it functions both as a full-wave rectifier and a frequency doubler. Since analog design allows the use of multiple bias voltages, we believe that this principle can be generalized as follows. When the OPC amplifier is biased such that V bias < V min (V min is the minimum conduction point), the small-signal transconductance g m = I d / V gs is negative, leading to a negative gain ( V out / V gs = R load I d / V gs = R load g m ). Similarly, if V bias > V min, the transconductance is positive and the gain of the OPC amplifier is positive. When only a single bias voltage V bias = V min is chosen, a small signal input sees a positive gain in its positive phase and a negative in its negative phase, resulting in both full-wave rectification and frequency doubling. When two bias voltages are used, it is possible to use a large square-wave signal as the input such that the square-wave switches the OPC amplifier between positive and negative gain modes. In this configuration, the OPC amplifier functions as a phase modulator with applications to both analog and digital electronics. For example, if the square-wave is actually the data stream, and it modulates the phase of a high-frequency carrier sine signal, the OPC amplifier realizes binary phase shift keying (BPSK). BPSK based on the OPC amplifier is illustrated in Figure 2(b), and we validate our proposed design using experimental data published for top-gated graphene transistors [15]. Traditionally, BPSK uses Si-based complex analog multipliers that not only require multiple transistors and/or filters but are also bandwidth-limited to 1GHz [17]. In contrast, our proposed OPC amplifier based on ambipolar devices requires only one transistor and can operate at potentially very high frequencies if fabricated with ambipolar devices such as graphene and carbon nanotubes, which have been predicted to achieve an inherent cut-off frequency f T greater than 1 THz [18, 19]. Similarly, the OPC amplifier can also be used in other multiplier-based applications such as phase detection. We believe that the simplicity of structures such as the OPC amplifier that promise lower parasitics and power consumption, as well as high spectral efficiency, merit further investigation of the applications of ambipolarity in applications such as quadrature and highorder PSK, frequency shift keying (FSK), analog-to-digital and digital-to-analog conversion, etc. 3 Digital circuits For digital applications, it has been proposed to control ambipolarity through the fabrication of an extra gate, usually termed the polarity gate. This was demonstrated early on for double-gate CNTFETs [7], and the first designs controlled the top and back gates separately to realize a universal reconfigurable 8-function gate [11]. More recently, it was proposed that the self-alignment fabrication process [2] could be used to realize top-gated ambipolar devices with independent gates as shown in Fig. 3(a) [12]. Here, D, S, and G are the conventional drain, source, and gate, while gate PG determines the polarity of the ambipolar transistor. A low/high voltage on PG results in p-type/n-type behavior, respectively, and the polarity of the transistor can be expressed as the XOR of the G and PG inputs in Boolean terms. This technology was used to explore in-field controllable dynamic logic [12] as well as static logic [13], and significant gains in area, power, and performance have been reported. The higher expressive power over conventional CMOS gates Yang and Mohanram: Rice University TREE12 2

3 Figure 2: (a) OPC amplifier (b) Waveforms for BPSK along with in-field programmability and regular layout motivate the realization of dense and regular manufacturable logic fabrics based on ambipolar transistors. We believe that the design principles for ambipolar logic can be generalized using the schematic in Figure 3(b). The ambipolar circuit style accepts regular inputs x 1,x 2,...,x n and control inputs c s,c 1,c 2,...,c n. The transistor networks N 1 and N 2 are duals of each other, following series-parallel rules consistent with conventional CMOS. In the simplest case, motivated by the tiny-xor [21], the input c s (c s ) controls the polarity of the supply rail (ground rail) and the polarity gates of all the transistors in N 1 (N 2 ). If c s is high, the supply rail is high, the ground rail is low, the transistors in N 1 are p-type, and the transistors in N 2 are n-type. Based on this, the circuit in Fig. 3(c) implements the function f 1 = (x 1 x 2 ). Similarly, if c s is low, the circuit implements the function f 2 = (x 1 + x 2 ). The circuit thus implements c s f 1 + c sf 2, i.e., c s (x 1 x 2 ) + c s(x 1 + x 2 ). Depending on the level of flexibility, i.e., the number of double-gated ambipolar transistors whose control inputs c i can be controlled individually to determine the polarity of the transistors driven by input x i, it is possible to realize more complex Boolean functions with embedded XORs. This is illustrated for the example in Fig. 3(d), where the complex function c s (x 1 c 1 ) + c s(x 1 c 1 ), i.e., c s x 1 c 1 is realized using only 4 transistors. Such gates are significantly more compact and expressive than comparable CMOS forms. We believe that as fabrication techniques advance and as multi-gate device technologies mature, polarity controllable logic will open up new opportunities in circuit design, logic synthesis based on XOR sum-of-product representations, and in-field programmable logic fabrics. 4 Challenges and opportunities Whereas ambipolar behavior that enables transistor conduction in either gate polarity has been considered undesirable in next-generation devices, there is mounting evidence that the ability to control ambipolarity presents new design opportunities in both the analog and digital domains. Although several challenges, including (i) the ability to reduce parametric variations, (ii) fabricating additional polarity gates, and (iii) modeling and simulation remain, they are concurrently being addressed by the device and CAD communities. In summary, ambipolarity is here to stay and this position paper strongly argues for further investigation of its applicability in both analog and digital domains. References [1] S. Heinze et al., Unexpected scaling of the performance of carbon nanotube Schottky-barrier transistors, Physical Review B, vol. 68, p , 23. Yang and Mohanram: Rice University TREE12 3

4 Figure 3: (a) Double-gate polarity controllable ambipolar FET, (b) polarity controllable ambipolar logic, (c) implementation of c s (x 1 x 2 ) + c s(x 1 + x 2 ), and (d) implementation of c s (x 1 c 1 ) + c s(x 1 c 1 ) = c s x 1 c 1 [2] K. S. Novoselov et al., Electric field effect in atomically thin carbon films, Science, vol. 36, no. 5696, pp , 24. [3] A. Colli et al., Top-gated silicon nanowire transistors in a single fabrication step, ACS Nano, vol. 3, no. 6, pp , 29. [4] S. Koo et al., Enhanced channel modulation in dual-gated silicon nanowire transistors, Nano Letters, vol. 5, no. 12, pp , 25. [5] A. Dodabalapur et al., Organic heterostructure field-effect transistors, Science, vol. 269, no. 523, pp , [6] J. H. Schön et al., Ambipolar pentacene field effect transistors and inverters, Science, vol. 287, no. 5455, pp , 2. [7] Y.-M. Lin et al., High-performance carbon nanotube field-effect transistor with tunable polarities, IEEE Trans. Nanotechnology, vol. 4, pp , 25. [8] X. Wang et al., N-doping of graphene through electrothermal reactions with ammonia, Science, vol. 324, no. 5928, pp , 29. [9] Y. Lin et al., Ambipolar-to-unipolar conversion of carbon nanotube transistors by gate structure engineering, Nano Letters, vol. 4, no. 5, pp , 24. [1] A. Javey et al., Carbon nanotube field-effect transistors with integrated ohmic contacts and high-k gate dielectrics, Nano Letters, vol. 4, pp , 24. [11] I. O Connor et al., CNTFET modeling and reconfigurable logic-circuit design, IEEE Trans. on Circuits and Systems I, vol. 54, no. 11, pp , 27. [12] M. H. B. Jamaa et al., Programmable logic circuits based on ambipolar CNFET, in Proc. Design Automation Conference, pp , 28. [13] M. H. B. Jamaa et al., Logic circuits with ambipolar CNTFETs: novel opportunities for multi-level logic synthesis, in Design Automation and Test in Europe, pp , 29. Yang and Mohanram: Rice University TREE12 4

5 [14] H. Wang et al., Graphene frequency multipliers, IEEE Electron Device Letters, vol. 3, no. 5, pp , 29. [15] I. Meric et al., Current saturation in zero-bandgap, top-gated graphene field-effect transistors, Nature Nanotechnology, vol. 3, pp , 28. [16] G. Fiori et al., Performance comparison of graphene nanoribbon Schottky barrier and MOSFETs, in Intl. Electron Devices Meeting, pp , 27. [17] B. Tzeng et al., A 1-17 GHz InGaP-GaAs HBT MMIC analog multiplier and mixer with broad-band inputmatching networks, IEEE Trans. on microwave theory and techniques, no. 11, pp , 22. [18] P. J. Burke, AC performance of nanoelectronics: Towards a ballisitic THz nanotube transistor, Solid-State Electronics, vol. 48, pp , 24. [19] Y. Lin et al., Operation of graphene transistors at gigahertz frequencies, Nano Lett., vol. 9, no. 1, pp , 29. [2] A. Javey et al., Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays, Nano Letters, vol. 4, no. 7, pp , 24. [21] J. Rabaey, Digital integrated circuits: a design perspective. Prentice Hall, Yang and Mohanram: Rice University TREE12 5