Reconfigurable Si-Nanowire Devices

Transcription

1 Reconfigurable Si-Nanowire Devices

2 André Heinzig, Walter M. Weber, Dominik Martin, Jens Trommer, Markus König and Thomas Mikolajick

3 log I d Present CMOS technology ~ 88 % of IC market covered by CMOS n- / p- FETs alternated to constrain energy consumption to the switching event n- and p- FETs differ in technology (doping, device dimensions, strain, gate) Limited to static and single switch - function VG High-k dielectric metal / poly Si V G 0 V Inverter, modified from S. Selberherr TU Wien Simplified MOSFET [W.M.Weber]

4 log size (L G ) Future CMOS technology Scaling 200 µm 22 nm Downscaling difficulties in: Fabrication (e.g. doping profiles, lithography) Performance (e.g. SCE, doping variability) Atomic scale End of classical scaling Physical limits Explore alternative solutions to yield more functions / values per building block Our approach: Devices Based on Silicon Nanowires Bottom-up grown nanowires as a vehicle

5 Nanowire device fabrication SiH 4 Au VLS-growth Silicidation <112> on SiO 2 <110> on Si Au/Si <200 nm> Ø = 7-30 nm Si-NW Sharp ME-SC interface (Schottky contact) Ni 100 nm [W.M. Weber, et al. IWEPNM 2006 PSSb 243, (2006)] [W.M. Weber et al. Nano Lett. 6, 2660 (2006)]

6 Nanowire field effect transistor (back gate) Ni Ni S NiSi 2 Si NiSi 2 D SiO 2 n ++ - Si G NiSi 2 Si NiSi 2 nanowire heterostructure intruded source, drain (S/D) - contacts down-scaled length of active region field enhancement at metal-s/d -interface well defined Schottky junctions common back gate

7 drain current I D [A] Nanowire field effect transistor (back gate) Schottky barrier FET working princible: Field induced band bending L g = 1140 nm Ø = 17 nm Injection of both electrons and holes: ambipolar behavior t OX = 20 nm Si NiSi 2 V G Ni 1x10-6 1x10-7 1x10-8 1x10-9 1x10-10 I on = 100 na I on /I off 10 6 V G gate voltage V G [V]

8 Drain - current - maps Analyzing transport mechanism by scanning gate microscopy (SGM) S Scan direction D + SiO 2 G Turn device on with electron tunnel current + Enhance on-current by flushing holes at drain In contrast to a MOSFET a point potential selectively controls electron / hole transport [D. Martin, et al. Phys. Rev. Lett. 107, (2011)]

9 Reconfigurable silicon nanowire transistor (RFET) Drain Si Source Program gate NiSi 2 SiO 2 shell Control gate Si SiO 2 NiSi 2 20 nm [A. Heinzig, et. al Nano Lett 12, 119 (2012)]

10 Reconfigurable silicon nanowire transistor (RFET) Drain Si PG NiSi 2 Source shell CG d=20 nm, SiO 2 = 10 nm, <112> p-program Transfer characteristic I on /I off 1E+9 SSL 93 mv/dec Same FET provides p- and n- type transport: functionality enhanced device n-program [A. Heinzig, et. al Nano Lett 12, 119 (2012)]

11 Devices for circuit implementation Useful CMOS integration requires equivalent p- and n- operation currents Conventional Reconfigurable one physical structure for n- and p-type FET top view Classical CMOS: p-mosfet approx. double width than n-mosfet FET top view no independent optimization! Reconfigurable CMOS electronics: Symmetry by equal design and layout for n-fet and p-fet

12 Dually active nanowire with equal electron and hole transport symmetric RFET NW diameter = 12 nm SiO 2 -thickn. = 8 nm compressive strain: 1.29 GPa [A. Heinzig, et. al Nano Lett 13, (2013)]

13 Reconfigurable CMOS electronics Single Nanowire Inverter [A. Heinzig, et. al Nano Lett 13, (2013)]

14 CMOS reconfigurable circuit Single nanowire Inverter V out V in Reconfiguration Symmetric switching (V DD /2) I DD only while switching CMOS functionality

15 Conventional (8 FETs) Reconfigurable (4 FETs) Conventional vs. Reconfigurable: NAND NOR RFET electronics Reduced hardware complexity (NAND/NOR: 4 instead of 8 FETs) [A. Heinzig, et. al Nano Lett 13, (2013)]

16 Project ReproNano Summary Conventional CMOS static p- and n-devices, expected end of scaling Silicon nanowire transistors bottom up fabrication, SBFETs, Ambipolar Transport analysis carrier type injection controlled by point potential at Schottky barriers p-program n-program Reconfigurable nanowire transistor (RFET) p- and n- type behavior on same devices no doping required Reconfigurable nanowire electronic CMOS functionality, reconfigurability (Inverter, NAND/NOR)

17 Visit us at SEMICON Science Park (Hall 2) Booth: Booth: Thank you! andre.heinzig@namlab.com

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19 log I d Backup RFET a device for future electronics? p 1. Functionality enhanced 2. Energy efficiency - reconfigurable (1 RFET provides p- and n-fet) - complementary integration (p- and n-type FETs) V G 0 V n 3. Cost-effective and reliable fabrication - compatible with silicon technology, suppression of doping variability, top down processing 4. Scalable - enhanced electrostatic geometry, dopant free, but additional wiring? Add-on to standard CMOS

20 Backup SiO 2 (2) (1) (2) (1) Ni Ni E 0 = 5kV Ni 100 nm Ni-diffusion length up to various µm EDX: Interface has abruptness in the nm scale [Weber W. M. et al. Nano Lett. 6, 2660 (2006)]

21 Backup Si-NW Ni SiO 2 SiNW US-treatment NW suspension Contact NWs with Ni (electro-less plating or EBL and deposition) Embeds NWs Contact to an unexhaustible Ni reservoir SiO 2 Ni

22 [Weber W. M. et al. Nano Lett. 6, 2660 (2006)] [K.N. Tu Ann. Rev. Mater. Sci. 1985, 15: 147] Backup Longitudinal silicidation: TEM Si-NW NiSi 2 <1 1 0> Ni 100 nm <1 1 0> NiSi 2 vs. 4nm Bulk Ni / Si reaction Sharp metallurgical interface compared to patchy bulk interface Important for electronic characteristic

23 Backup Strategy for a symmetric reconfigurable device RFET φn T w Eg Alter n- and p- tunneling transmission by engineering cystal direction and strain Si-NW crstal direction <110> most sensitive direction to strain [Y.-M. Niquet et al., Nano Lett. 12, (2012)] Use of thinner Si body to enhance contribution of tunneling currents