Towards a Reconfigurable Nanocomputer Platform

Transcription

1 Towards a Reconfigurable Nanocomputer Platform Paul Beckett School of Electrical and Computer Engineering RMIT University Melbourne, Australia 1 The Nanoscale Cambrian Explosion Disparity: Widerangeof emerging non-si technologies Diversity: Many new device options in CMOS, GaAs and other non-si NSC-1 2 1

2 Example Nanoscale Devices Disparity Silicon SOI Si-Ge Dual-gate Vertical FET Ballistic nano-fet RTD/ HFET RTT logic & memory Multivalued logic nanopipelining Heterojunction Nanotube CNT C60 logic &memory Nanotube array logic Largebandgap devices (AlN, BN) Molecular Rotaxane molecular x-bar CAEN Coulombcoupled optically pumped nanodevices DNA Magnetic Quantum dot Quantum diffraction FET Quantum interference devices surface superlattices RSFQ GMR/ CMR MQCA Hybrid- Hall effect Molecular nanomagnetics Magnetic RTD Q-Well 3 The Ideal Nanocomputer Platform? Very large, scalable with rich, local connectivity Built from simple devices that exhibit: High functionality (?) Gain > 1 Static (at least) and preferably non-volatile operation (Very) low power density Room temperature operation Reliable and fault tolerant Preferably no intrinsic reliance on any form of global signal (e.g. a master clock) Reconfigurable in operation, with little or no performance penalty 4 2

3 Three Example Nanoscale Systems 1. Multi-valued SRAM Based Platform RTD multi-valued RAM Dual-gate transistors 2. Phase Transition Device Based Platform Resistive thin-films 3. A Nano-Magnetic Platform Double spin-filter junction 5 Multi-valued SRAM Based Platform metal-insulator tunnel transistor (MITT) gate voltage modulates the tunnel barrier compatible with current fabrication processes can be buried in oxide layer Proposed dual-gate increases functionality Low-overhead reconfiguration Source Top Gate gate insulator gate insulator Back Gate substrate A 0.0V -0.1V -0.2V Drain Tunnel Insulator -0.3V C -0.4V Second-Gate Voltage B V G1 6 V DD R L V G2 3

4 Multi-valued SRAM Based Platform 3-state memory (Wei & Lin) V 1-3 matched by adjusting RTD barrier layer thicknesses Word Line V DD3 I I D P Word Line R L insulator Bit Line RTDs RTDs VDD VSS VSS VDD Out 1 Substrate 1 Gnd Substrate 2 R L it Line V SS I V V SS V 1 V 2 V 3 7 V DD3 Ultimate dimensions 50nm ~3 x10 9 cells/cm 2 V D Non-volatility Chalcogenide Films Word Line Chalcogenide films act as fast non-volatile programmable resistor Compatible with current (CMOS) logic fabrication Scales well to nanoscale dimensions (20-30nm) Vertical integration SiO 2 Bit Line TiW Heater Al n <100nm n+ V A V SS p word line Polycrystalline Chalcogenide V dd plane internal routing top gate/input gate insulator tunnel insulator gate insulator back gate ground plane schottky metal bit line substrate layer 8 4

5 Double Spin-Filter Tunnel Junction Magnetoresistive tunnel device (Worledge & Geballe) Potentially very high GMR Formed from two different layers that are insulating but magnetic with unequal coercivities parallel nonmagnetic electrode pinned magnetic barrier free magnetic barrier nonmagnetic electrode Antiparallel pinned barrier free barrier J J E f d d 9 E f Vertical Double Spin-Filter Junction Resistance is varied between the inner pillar and the multiple outer conductors Requires ~20Ǻ films on vertical pillar No obvious candidates Thickness control and lattice matching will be important free layer inner conductor outer conductors (x 4) Substrate pinned layer a) Top View b) Side View c) Square Mesh Connections 10 5

6 Spin-Filter Based Platform RTD substrate adds non-linearity to effect logic VTT for isolation Junction densities in excess of 2 x /cm 2 possible RTD Vertical FET word line RTD RTD V DD tunnel junction BL BL BL gate dielectric vertical channel Conductive substrate 11 Spatial Computing Memory Hierarchy Tries to hide the cost of moving code and data items from one place to another in a processor system 3D memory (Zhang) Proposed as means memory and processing physically closer together memory layers Inter-level Dielectric IC substrate 3D ROM Zhang,

7 A 3D Reconfigurable Computing Platform Merged processor/ memory into 3D structure Reduced memory performance gap Extreme memory bandwidth Processing-in-memory; processing-is-memory memory/processor layers vertical interconnect base substrate 3D Processor/memory 13 Reconfigurable Nanoelectronic Devices? PRO Maximizes utility of small devices Reconfiguration overheads kept small (Mostly) evolving from existing techniques Compatible with logic synthesis systems CON Can they be built? Is the added complexity justified vs. (say) molecular approach? Will they efficiently support high-performance computer architectures 14 7

8 What s Next? Simulation of nano-magnetic materials Characterization of typical junctions e.g. tunneling conductance Simulation of GMR-based array platform Development of Spatial Computing techniques suited to this platform 15 Andinthelongterm? Decimation followed by diversification (Gould) Test against the environment ease of fabrication, cost, ease of use etc. Extinction for some, consolidation and growth for others 16 8

9 Towards a Reconfigurable Nanocomputer Platform Thank You Paul Beckett 17 9