EE 330 Lecture 7. Design Rules
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1 EE 330 Lecture 7 Design Rules
2 Last time: Response time of logic gates A Y C L t R C HL SWn L t R C LH SWp L C L proportional to #gates driven to avg input cap of gates R SW proportional length/width
3 Last time: NMOS Transistor Drain Top View Source Drain Gate Gate Source Symbol for n-channel MOSFET Source Gate Drain n-type Bulk n+-type p-type p+-type SiO 2 (insulator) Cross-Sectional View POLY (conductor) n-channel MOSFET
4 3D view: source gate drain Bulk Source Gate Drain n-type n+-type p-type p+-type SiO 2 (insulator) POLY (conductor) n-channel MOSFET
5 PMOS Transistor Source Gate Drain Drain Bulk Gate Cross-Sectional View Source p-channel MOSFET Symbol for p-channel MOSFET n-type n+-type Top View Source Drain p-type p+-type Gate SiO 2 (insulator) POLY (conductor)
6 Stick Diagrams It is often necessary to obtain information about placement, interconnect and physical-layer structure Stick diagrams are often used for small component-count blocks Approximate placement, routing, and area information can be obtained rather quickly with the use of stick diagrams
7 Stick Diagrams Metal 1 poly n-diffusion p-diffusion Metal 2 Contact Additional layers can be added and color conventions are peronal
8 Stick Diagram V DD A B A B A B A stick diagram is not a layout but gives the basic structure (including location,, orientation and interconnects) that will be instantiated in the actual layout itself Modifications can be made much more quickly on a stick diagram than on a layout Iteration may be needed to come up with a good layout structure
9 A B Stick Diagram Alternate Representations A B A B A B
10 VDD VSS
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13 Semiconductor Fabrication Technology Technology Files Fabrication CAD Provide Information About Process Process Flow (Fabrication Technology) Circuits Model Parameters Design Rules Serve as Interface Between Design Engineer and Process Engineer Insist on getting information that is deemed important for a design Limited information available in academia Foundries often sensitive to who gets access to information Customer success and satisfaction is critical to foundries Devices
14 Design Rules Technology Files Process Flow (Fabrication Technology) (will discuss next ) Model Parameters (will discuss in substantially more detail after device operation and more advanced models are introduced) First A preview of what the technology files look like!
15 Typical Design Rules
16 Typical Design Rules (cont)
17 Typical Design Rules (cont)
18 Typical Design Rules (cont)
19 Typical Process Description
20 Typical Process Description (cont)
21 Typical Process Description (cont)
22 Typical Model Parameters
23 Typical Model Parameters (cont)
24 Typical Model Parameters (cont)
25 Typical Model Parameters (cont)
26 Typical Model Parameters (cont)
27 Typical Model Parameters (cont) 98 parameters in this BSIM Model!
28 Typical Model Parameters (cont)
29 Design Rules Technology Files Process Flow (Fabrication Technology) (will discuss next ) Model Parameters (will discuss in substantially more detail after device operation and more advanced models are introduced)
30 Design Rules Give minimum feature sizes, spacing, and other constraints that are acceptable in a process Very large number of devices can be reliably made with the design rules of a process Yield and performance unpredictable and often low if rules are violated Compatible with design rule checker in integrated toolsets
31 Design Rules and Layout consider transistors Layer Map Drain Drain n-well bulk CMOS Process Gate Gate p-active n-active Source Source Poly 1 Metal 1 n-well L W L W contact D G S D G S Layout Layout Layout always represented in a top view in two dimensions
32 Design Rules and Layout consider transistors Drain Drain Layer Map p-active Gate Gate n-active Poly 1 Metal 1 Source Source n-well contact L W L W D G Layout S D G Layout S Everything useful in channel region. All other features just overhead that degrades performance
33 Design Rules L W D G Design rules give minimum feature sizes and spacings S Designers generally do layouts to minimize size of circuit subject to design rule constraints (because yield, cost, and performance usually improve)
34 Design Rules and Layout consider transistors Drain Drain Layer Map p-active n-active Gate Gate Bulk Poly 1 Metal 1 Source Source n-well contact L W D G S B Bulk connection needed Single bulk connection can often be used for several (many) transistors D G S
35 Design Rules and Layout consider transistors Drain Drain Layer Map p-active Gate Gate Bulk n-active Poly 1 Source Source Metal 1 n-well contact D G S Bulk connection needed Single bulk connection can often be used for several (many) transistors if they share the same well B D G S
36 Design Rules and Layout (example) A Y Logic Circuit V DD A M 2 M 4 Y M 1 M 3 W=0.9u L=0.6u Circuit Schematic (Including Device Sizing) A Y Stick Diagram
37 Design Rules (example) A Y V DD Layer Map A Y p-active n-active Poly 1 Metal 1 V SS (GND) Layout n-well contact
38 Design Rules (example) Polygons merged in Geometric Description File (GDF) Separate rectangles generally more convenient to represent
39 Design Rules (example) Design rules must be satisfied throughout the design DRC runs incrementally during layout in most existing tools to flag most problems DRC can catch layout design rule errors but not circuit connection errors
40 Design Rules (example) What is wrong with this layout? Bulk connections missing!
41 D D Design Rules (example) G G B V DD S n-channel S S S A Y G G B D p-channel D Actually 4-terminal device V SS Note diffusions needed for bulk connections Note n-well connections increase area a significant amount Note n-wells are both connected to V DD in this circuit
42 Design Rules (example) Layout with shared p-well reduces area
43 Design Rules (example) Shared p-active can be combined to reduce area Shared n-active can be combined to reduce area
44 Design Rules Design rules can be given in absolute dimensions for every rule Design rules can be parameterized and given relative to a parameter Makes movement from one process to another more convenient Easier for designer to remember Some penalty in area efficiency Often termed λ-based design rules Typically λ is ½ the minimum feature size in a process
45 Design Rules See for design rules
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50 Design Rules See for design rules Some of these files are on class WEB site SCMOS Rules Updated Sept 2005.pdf Mosis Rules Pictorial.pdf
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EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1
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