EE 330 Lecture 5. Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic

Transcription

1 EE 330 Lecture 5 Other Logic Styles complex logic gates pass transistor logic Improved evice Models

2 Review from Last Time MOS Transistor Qualitative iscussion of n-channel Operation Source Gate rain rain ulk Gate Cross-Sectional View n-channel MOSFET Source n-type n+-type Top View Source rain p-type p+-type Gate SiO 2 (insulator) POL (conductor) esigner always works with top view Complete Symmetry in construction between rain and Source

3 Review from Last Time MOS Transistor Comparison of Operation rain rain Gate Gate Source Source G = 0 G = 1 G = 0 G = 1 S S S S Source assumed connected to (or close to) ground Source assumed connected to (or close to) V and oolean G at gate is relative to ground

4 Other logic circuits Other methods for designing logic circuits exist Insight will be provided on how other logic circuits evolve Several different types of logic circuits are often used simultaneously in any circuit design

5 Pull-up and Pull-down Networks V V PUN GN PN GN PU network comprised of p-channel device and tries to pull to V when conducting P network comprised of n-channel device and tries to pull to GN when conducting One and only one of these networks is conducting at the same time

6 Pull-up and Pull-down Networks V V PUN C C PN PU network comprised of p-channel devices P network comprised of n-channel devices One and only one of these networks is conducting at the same time

7 Pull-up and Pull-down Networks V V C PUN C PN PU network comprised of p-channel device P network comprised of n-channel device One and only one of these networks is conducting at the same time

8 Pull-up and Pull-down Networks In these circuits, the PUN and PN have the 3 interesting characteristics V 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time X n PUN PN What are V H and V L? What is the power dissipation? How fast are these logic circuits?

9 Consider the inverter What are V H and V L? What is the power dissipation? How fast are these logic circuits? Use switch-level model for MOS devices V V

10 Consider the inverter What are V H and V L? What is the power dissipation? How fast are these logic circuits? Use switch-level model for MOS devices V V H =V V L =0 I =0 thus P H =P L =0 t HL =t LH =0 (too good to be true?)

11 Pull-up and Pull-down Networks For these circuits, the PUN and PN have 3 interesting characteristics V Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time PUN What are V H and V L? V H =V, V L =0 (too good to be true?) What is the power dissipation? P H =P L =0 (too good to be true?) How fast are these logic circuits? t HL =t LH =0 (too good to be true?) X n PN These 3 properties are inherent in oolean circuits with these 3 characteristics

12 Pull-up and Pull-down Networks Three key characteristics of Static CMOS Gates 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time Three properties of Static CMOS Gates (based upon simple switch-level model) 1. V H =V, V L =0 (too good to be true?) X n V PUN PN 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in oolean circuits with these 3 characteristics

13 Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate n-input NN gate V V X 1 X 1 X 2 X n X 2 X 1 X n X 2 X 1 X 2 X n X n

14 Pull-up and Pull-down Networks Concept can be extended to arbitrary number of inputs n-input NOR gate V n-input NN gate V X 1 X 1 X 2 X n X 2 X 1 X n X 2 X 1 X 2 X n X n 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time

15 Pull-up and Pull-down Networks V X 1 V X 2 X n PUN X 1 X 2 X n X n n-input NOR gate PN X 1 X 2 X n X 1 X 2 V 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time X n n-input NN gate V H =V, V L =0 P H =P L =0 t HL =t LH =0

16 Nomenclature V V X 1 X 2 X 1 X 2 X n X 1 X n X 2 X 1 X 2 X n X n n-input NOR gate n-input NN gate In this class, logic circuits that are implemented by interconnecting multipleinput NN and NOR gates will be referred to as Static CMOS Logic Since the set of NN gates is complete, any combinational logic function can be realized with the NN circuit structures considered thus far Since the set NOR gates is complete, any combinational logic function can be realized with the NOR circuit structures considered thus far Many logic functions are realized with Static CMOS Logic and this is probably the dominant design style used today!

17 Example 1: Circuit Structures Circuit esign How many transistors are required to realize the function F C in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available.

18 Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available. Solution: C F 20 transistors and 5 levels of logic

19 How many transistors are required to realize the function in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available. C F Solution (alternative): From basic oolean Manipulations C C F C 1 F F 8 transistors and 3 levels of logic Example 1:

20 Example 1: How many transistors are required to realize the function F C in a basic CMOS process if static NN and NOR gates are used? ssume, and C are available. Solution (alternative): From basic oolean Manipulations F 1 C F F 6 transistors and 2 levels of logic

21 Example 2: XOR Function = widely-used 2-input Gate Static CMOS implementation = + 22 transistors 5 levels of logic elays unacceptable (will show later) and device count is too large!

22 Example 3: C Standard Static CMOS Implementation C 3 levels of Logic 16 Transistors if asic CMOS Gates are Used Can the same oolean functionality be obtained with less transistors?

23 Observe: V C C C Significant reduction in transistor count and levels of logic for realizing same oolean function Termed a Complex Logic Gate implementation Some authors term this a compound gate

24 Complex Logic Gates Pull-up Network C V Pull-down Network C C

25 Complex Gates V Pull up and pull down network never both conducting One of the two networks is always conducting C C

26 Complex Gates Nomenclature: V PUN X n PN When the logic gate shown is not a multiple-input NN or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Gate Complex Logic Gates also implement static logic functions and some authors would refer to this as Static CMOS Logic as well but we will make the distinction and refer to this as Complex Logic Gates

27 Complex Gates V PUN X n PN Complex Gate esign Strategy: 1. Implement in the PN 2. Implement in the PUN (must complement the input variables since p- channel devices are used) ( and often expressed in either SOP or POS form)

28 XOR in Complex Logic Gates = Will express and in standard SOP or POS form

29 XOR in Complex Logic Gates = = + = + = = + +

30 XOR in Complex Logic Gates = + = + + PN PUN

31 XOR in Complex Logic Gates V = + = transistors and 2 levels of logic Notice a significant reduction in the number of transistors required

32 XOR in Complex Logic Gates = + = + + Multiple PU and P networks can be used =

33 Complex Logic Gate Summary: V PUN X n PN If PUN and PN satisfy the characteristics: 1. PU network comprised of p-channel device 2. P network comprised of n-channel device 3. One and only one of these networks is conducting at the same time Properties of PU/P logic of this type (with simple switch-level model): Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model)

34 Consider Standard CMOS Implementation 2 levels of Logic 6 Transistors if asic CMOS Gates are Used asic noninverting functions generally require more complexity if basic CMOS gates are used for implementation

35 Pass Transistor Logic V R Requires only 2 transistors rather than 6 for a standard CMOS gate (and a resistor).

36 Pass Transistor Logic R Even simpler pass transistor logic implementations are possible Requires only 1 transistor (and a resistor). Will see later that the area of a single practical resistor for this circuit may be comparable to that needed for hundreds or even thousands of transistors

37 Pass Transistor Logic R May be able to replace resistor with transistor (one of several ways shown) ut high logic level can not be determined with existing device model (or even low logic level for circuit on right) Power dissipation can not be determined with existing device model for circuit on right etter device model is needed (Power? Signal Swing? Speed?)

38 Pass Transistor Logic R 6 transistors, 1 resistor, two levels of logic (the 4 transistors in the two inverters are not shown)

39 Pass Transistor Logic R R 2 transistors, 1 resistor, one level of logic

40 Pass Transistor Logic R Requires only 1 transistor (and a resistor) - Pass transistor logic can offer significant reductions in complexity for some functions (particularly noninverting) - Resistor may require more area than several hundred or even several thousand transistors - Signal levels may not go to V or to 0V - Static power dissipation may not be zero - Signals may degrade unacceptably if multiple gates are cascaded - resistor often implemented with a transistor to reduce area but signal swing and power dissipation problems still persist - Pass transistor logic is widely used

41 Logic esign Styles Several different logic design styles are often used throughout a given design (3 considered thus far) Static CMOS Complex Logic Gates Pass Transistor Logic The designer has complete control over what is placed on silicon and governed only by cost and performance New logic design strategies have been proposed recently and others will likely emerge in the future The digital designer needs to be familiar with the benefits and limitations of varying logic styles to come up with a good solution for given system requirements

42 MOSFET Modeling rain rain Gate Gate Simple model of MOSFET was developed (termed switch-level model) Source Simple gates designed in CMOS Process were introduced Some have zero power dissipation Some have or appeared to have rail to rail logic voltage swings ll appeared to be Infinitely fast Logic levels of some can not be predicted with simple model Simple model is not sufficiently accurate to provide insight relating to some of these properties MOSFET modeling strategy hierarchical model structure will be developed generally use simplest model that can be justified Source

43 MOS Transistor Models 1, Switch-Level model rain rain Gate Gate Source Source G = 0 G = 1 G = 0 G = 1 dvantages: Simple, does not require understanding of semiconductor properties, does not depend upon process, adequate for understanding basic operation of many digital circuits S S S S Limitations: oes not provide timing information (surfaced when looking at static CMOS circuits, and several others that have not yet become apparent from the applications that have been considered) and can not support design of resistor used in Pass Transistor Logic

44 Improved evice Models With the simple switch-level model, it was observed that basic static CMOS logic gates have the following three properties: evice Models and Operation Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model) It can be shown that the first two properties are nearly satisfied in actual fabricated circuits but though the circuits are fast, they are observably not arbitrarily fast Will now extend switch-level model to predict speed of basic gates

45 Recall MOS Transistor Qualitative iscussion of n-channel Operation ulk Source Gate rain rain Gate n-channel MOSFET Source G = 0 G = 1 S S

46 MOS Transistor Qualitative iscussion of n-channel Operation ulk Source Gate rain rain G Gate n-channel MOSFET Source G = 0 G = 1 S S

47 MOS Transistor Qualitative iscussion of n-channel Operation Source Gate rain ulk Insulator rain For V GS small n-channel MOSFET Gate ulk Source Gate rain Source ulk Insulator Resistor For V GS large n-channel MOSFET

48 MOS Transistor Qualitative iscussion of n-channel Operation ulk Source Gate rain Insulator rain For V GS small n-channel MOSFET Source Gate rain Gate ulk ulk Insulator Source For V GS large n-channel MOSFET Thin film resistor is electrically created Capacitance from gate to channel region is distributed Lumped capacitance much easier to work with

49 Improved Switch-Level Model rain Gate Source G C GS R SW V G Switch closed for V GS = 1 S Switch-level model including gate capacitance and channel resistance Still neglect bulk connection and connect the gate capacitance to the source

50 Improved Switch-Level Model rain Gate G = 1 G = 0 Source n-channel S Switch-level model S G C GS R SW V GS Switch closed for V GS = large lt: switch closed for G = 1 Switch-level model including gate capacitance and channel resistance S

51 Improved Switch-Level Model rain Gate G = 0 G =1 Source p-channel S S Switch-level model G C GS R SW V GS S Switch closed for V GS large and neg lt: If S near V, closed for G=0 Switch-level model including gate capacitance and channel resistance

52 Improved Switch-Level Model rain Gate G Source R SW C GS V GS Switch closed for G =1 S Switch-level model including gate capacitance and channel resistance C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C GS 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C GS and R SW

53 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf.01uf rea allocations shown to relative scale:

54 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf 10fF 1fF.01uf 1pf rea allocations shown to relative scale: Not enough information at this point to determine whether this very small capacitance can be neglected Will answer this important question later

55 rain Model Summary Gate 1, Switch-Level model Source G = 1 G = 0 S S 2, Improved switch-level model G C GS R SW V G S Switch closed for V GS = large Switch open for V GS = small S Other models will be developed later

56 End of Lecture 5