Lecture 0: Introduction

Size: px
Start display at page:

Download "Lecture 0: Introduction"

Transcription

1 Introduction to CMOS VLSI Design Lecture : Introduction David Harris Steven Levitan Harvey Mudd College University of Pittsburgh Spring 24 Fall 28

2 Administrivia Professor Steven Levitan TA: Bo Zhao Syllabus Approximate subject to change Office Hours & Lab Assistant Hours Labs, Exams, and Project Grading Collaboration, yes Cheating, No Textbook: Harris and Weste Other refrerences on line and on reserve in Library Several Fundamental Ideas and many many many details - take good notes : Introduction CMOS VLSI Design Slide 2 2

3 Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip : Introduction CMOS VLSI Design Slide 3 3

4 Deconstructing a Computer System : Introduction 4 Steven Levitan 9 Nov

5 Deconstructing a Computer System : Introduction 5 clean dell computer.jpg Steven Levitan 9 Nov

6 Deconstructing a Computer System : Introduction 6 Steven Levitan 9 Nov

7 Deconstructing a Computer System : Introduction 7 Board_6.jpg Steven Levitan 9 Nov

8 Deconstructing a Computer System : Introduction 8 Steven Levitan 9 Nov

9 From Chips to DIPs Single die Slicing and Dicing Wafer : Introduction 9 From Steven Levitan 9 Nov

10 Going Back and Zooming In Quad Core Barcelona 27 : Introduction Steven Levitan 9 Nov 27

11 Going Back and Zooming In 22 22M Transistors 42mm 2 : Introduction Steven Levitan 9 Nov 27

12 Going Back and Zooming In 998 Pentium(II) 7.5M Transistors 8mm 2 : Introduction 2 Steven Levitan 9 Nov

13 Going Back and Zooming In K Transistors mm 2 : Introduction 3 Steven Levitan 9 Nov

14 Going Back and Zooming In 97 2K Transistor 44 2mm 2 : Introduction 4 Steven Levitan 9 Nov

15 Going Back and Zooming In ECL 3 input Gate Motorola 966 : Introduction 5 Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed Steven Levitan 9 Nov

16 Photomasks to Circuits Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed : Introduction 6 Weste & Harris CMOS VLSI Design Copyright 25 Pearson Addison-Wesley. All rights reserved. Steven Levitan 9 Nov

17 The Y Abstraction Spiral Start Here End Here Gajski & Kuhn : Introduction 7 Steven Levitan 9 Nov

18 MOS Technology GATE.6 um um Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed : Introduction 8 Steven Levitan 9 Nov

19 Patterned Materials Create Circuits Silicon Crystal N type Doping P type Doping : Introduction 9 Weste & Harris CMOS VLSI Design Copyright 25 Pearson Addison-Wesley. All rights reserved. Steven Levitan 9 Nov

20 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si : Introduction CMOS VLSI Design Slide 2 2

21 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) Si Si - Si Si Si + Si Si + As Si Si B - Si Si Si Si Si Si Si : Introduction CMOS VLSI Design Slide 2 2

22 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode : Introduction CMOS VLSI Design Slide 22 22

23 nmos Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal Source Gate Drain Polysilicon SiO 2 n+ n+ p bulk Si : Introduction CMOS VLSI Design Slide 23 23

24 nmos Operation Body is commonly tied to ground ( V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S D : Introduction CMOS VLSI Design Slide 24 24

25 nmos Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S D : Introduction CMOS VLSI Design Slide 25 25

26 pmos Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO 2 p+ p+ n bulk Si : Introduction CMOS VLSI Design Slide 26 26

27 Power Supply Voltage GND = V In 98 s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5,.8,.5,.2,., : Introduction CMOS VLSI Design Slide 27 27

28 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g = g = nmos g d d OFF d ON s s s d d d pmos g ON OFF s s s : Introduction CMOS VLSI Design Slide 28 28

29 Transistors as Switches Input voltage on the CMOS N Switch gate controls the current through the source/drain path D G S N Switch D This provides output voltage to drive next circuit. G S Series / Parallel paths provide and and or logic functions G D S D S G : Introduction 29 Steven Levitan 9 Nov

30 From Switches to Boolean Functions... Use the switching functions to provide paths to Vdd or GND Vdd is the source of all Truth (Vdd = = ) GND is the source of all Falsehood (GND == ) P-channel N-channel : Introduction 3 Steven Levitan 9 Nov

31 The Inverter True to False / False to True Converter / / : Introduction 3 Steven Levitan 9 Nov

32 CMOS Inverter A Y V DD A Y A Y GND : Introduction CMOS VLSI Design Slide 32 32

33 CMOS Inverter A A Y Y V DD OFF A= Y= ON GND : Introduction CMOS VLSI Design Slide 33 33

34 CMOS Inverter A A Y Y V DD ON A= Y= OFF GND : Introduction CMOS VLSI Design Slide 34 34

35 Series/Parallel Circuits => Logic +Vdd CMOS NAND (not AND) Gate A B Y Truth Table A B Y Y = A B = A + B : Introduction 35 Steven Levitan 9 Nov

36 CMOS NAND Gate A B Y A B Y : Introduction CMOS VLSI Design Slide 36 36

37 CMOS NAND Gate A B Y A= ON ON Y= OFF B= OFF : Introduction CMOS VLSI Design Slide 37 37

38 CMOS NAND Gate A B Y A= OFF ON Y= OFF B= ON : Introduction CMOS VLSI Design Slide 38 38

39 CMOS NAND Gate A B Y A= ON OFF Y= ON B= OFF : Introduction CMOS VLSI Design Slide 39 39

40 CMOS NAND Gate A B Y A= OFF OFF Y= ON B= ON : Introduction CMOS VLSI Design Slide 4 4

41 CMOS NOR Gate A B Y A B Y : Introduction CMOS VLSI Design Slide 4 4

42 3-input NAND Gate Y pulls low if ALL inputs are Y pulls high if ANY input is : Introduction CMOS VLSI Design Slide 42 42

43 3-input NAND Gate Y pulls low if ALL inputs are Y pulls high if ANY input is A Y B C : Introduction CMOS VLSI Design Slide 43 43

44 From Logic to Binary Math Truth tables for binary addition/subtraction etc. A B A AND Carry Sum B XOR Sum Carry Sum = A xor B Carry = A and B Are these Amino Acids? : Introduction 44 Steven Levitan 9 Nov

45 F = ^(AB + AC + BC) => Carry Cout C = A = B = + : Introduction 45 Steven Levitan 9 Nov

46 Chip Photomask Layout : Introduction 46 Steven Levitan 9 Nov

47 Latches for State Cross coupled, charge storage, etc. Save logic values, change under temporal control (clocks) Set QB Reset Q DATA N+ Inputs DATA N Outputs S R Q QB Q QB hold Illegal Are these (folded) proteins? Latch Control (Clock) : Introduction 47 Steven Levitan 9 Nov

48 Finite State Machines FSM s capture processes Input Inputs, outputs, state Out = F((in), State n ) Next State & Output Calculation Output State n+ = F(in, State n ) Like a Markov process Current State Latch S S5 S3 Is this a regulatory process? S2 If (state = ) and (input = A) then state <= 4, output <= 5 : Introduction 48 Steven Levitan 9 Nov

49 (Re) Composing : Introduction 49 Steven Levitan 9 Nov

50 Computer Micro Architecture Basic operation on triples A <= B + C; R[2] <= R[] op R[]. Data from Register File 2. Operations done by Arithmetic and Logic Unit 3. Data returned to Register File Instruction Register SRC SRC2 DEST Op CC Register File ALU Op ={add, sub, shift, and, or, etc} CC = {zero, neg, overflow, etc} : Introduction 5 Steven Levitan 9 Nov

51 Instruction Set OP Code Src Src2 Destination Op Code Memory Address Three (four) types of instructions:. Move Data to / from Memory locations, I/O and temporary registers 2. Compute Logical, fixed point, floating point, string, bits 3. Program Flow Branch, Jump, Subroutines 4. Mode Control Privileged modes, interrupts, memory mapping Four addresses (explicit/implicit) Source, Source2, Destination, Next (PC) B+C => A (and do next instruction) Instruction set and micro-architecture define the complete computing system : Introduction 5 Steven Levitan 9 Nov

52 von Neumann Architecture I/O CPU Control PC Accumulator IR Fetch/Execute Cycle MAR < PC MBR < MEM[MAR] Increment PC IR < MBR Interpret instruction in IR MAR MBR (now called 5 stage pipeline ) Memory Done as a FSM in Control Unit Is this just like EIS.. Is this a ribosome? : Introduction 52 Steven Levitan 9 Nov

53 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! : Introduction CMOS VLSI Design Slide 53 53

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

Transistors, Gates and Busses 3/21/01 Lecture #

Transistors, Gates and Busses 3/21/01 Lecture # Transistors, Gates and Busses 3/2/ Lecture #8 6.7 The goal for today is to understand a bit about how a computer actually works: how it stores, adds, and communicates internally! How transistors make gates!

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University

More information

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1 Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar

More information

Shorthand Notation for NMOS and PMOS Transistors

Shorthand Notation for NMOS and PMOS Transistors Shorthand Notation for NMOS and PMOS Transistors Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V ds = V d V s = V gs - V gd Source and drain are symmetric diffusion

More information

Layers. Layers. Layers. Transistor Manufacturing COMP375 1

Layers. Layers. Layers. Transistor Manufacturing COMP375 1 VLSI COMP375 Computer Architecture Middleware other CS classes Machine Language Microcode Logic circuits Transistors Middleware Machine Language - earlier Microcode Logic circuits Transistors Middleware

More information

Spiral 1 / Unit 8. Transistor Implementations CMOS Logic Gates

Spiral 1 / Unit 8. Transistor Implementations CMOS Logic Gates 18.1 Spiral 1 / Unit 8 Transistor Implementations CMOS Logic Gates 18.2 Spiral Content Mapping Spiral Theory Combinational Design Sequential Design System Level Design Implementation and Tools Project

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2019 Khanna Jack Keil Wolf Lecture http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Layers. Layers. Layers. Transistor Manufacturing COMP375 1

Layers. Layers. Layers. Transistor Manufacturing COMP375 1 Layers VLSI COMP370 Intro to Computer Architecture t Applications Middleware other CS classes High level languages Machine Language Microcode Logic circuits Gates Transistors Silicon structures Layers

More information

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Computer Architecture (TT 2012)

Computer Architecture (TT 2012) Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture

More information

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1 EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules

More information

ECE380 Digital Logic. Logic values as voltage levels

ECE380 Digital Logic. Logic values as voltage levels ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the

More information

Digital Systems Laboratory

Digital Systems Laboratory 2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing

More information

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: Digital Logic Circuits Chapter 3: Implementation Technology Curtis Nelson Chapter 3 Overview In this chapter you will learn about: How transistors are used as switches; Integrated circuit technology;

More information

ENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph

ENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph ENG2410 Digital Design CMOS Technology Fall 2017 S. reibi School of Engineering University of Guelph The Transistor Revolution First transistor Bell Labs, 1948 Bipolar logic 1960 s Intel 4004 processor

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline:

ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline: ECE 340 Lecture 37 : Metal- Insulator-Semiconductor FET Class Outline: Metal-Semiconductor Junctions MOSFET Basic Operation MOS Capacitor Things you should know when you leave Key Questions What is the

More information

Lecture 4 - Digital Representations III + Transistors

Lecture 4 - Digital Representations III + Transistors Lecture 4 - Digital Representations III + Transistors Video: Seems like a natural extension from images no? We just have a new dimension (time) Each frame is just an image made up of pixels Display n frames

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

Investigation on Performance of high speed CMOS Full adder Circuits

Investigation on Performance of high speed CMOS Full adder Circuits ISSN (O): 2349-7084 International Journal of Computer Engineering In Research Trends Available online at: www.ijcert.org Investigation on Performance of high speed CMOS Full adder Circuits 1 KATTUPALLI

More information

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer

Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Design of Low power and Area Efficient 8-bit ALU using GDI Full Adder and Multiplexer Mr. Y.Satish Kumar M.tech Student, Siddhartha Institute of Technology & Sciences. Mr. G.Srinivas, M.Tech Associate

More information

CS/ECE 5710/6710. Composite Layout

CS/ECE 5710/6710. Composite Layout CS/ECE 5710/6710 Introduction to Layout Inverter Layout Example Layout Design Rules Composite Layout Drawing the mask layers that will be used by the fabrication folks to make the devices Very different

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

Introduction to Computer Engineering EECS 203 dickrp/eecs203/ Grading scheme. Review.

Introduction to Computer Engineering EECS 203  dickrp/eecs203/ Grading scheme. Review. Introduction to Computer Engineering EECS 203 http://ziyang.eecs.northwestern.edu/ dickrp/eecs203/ Grading scheme Instructor: Robert Dick Office: 77 Tech Email: dickrp@northwestern.edu Phone: 847 467 2298

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2017 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN

VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN Peter M. Maurer ENG 118 Department of Computer Science & Engineering University of South Florida Tampa, FL 33620 1. The Nature of licon

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

Very Large Scale Integration (VLSI)

Very Large Scale Integration (VLSI) Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell

More information

Low Power 8-Bit ALU Design Using Full Adder and Multiplexer

Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Gaddam Sushil Raj B.Tech, Vardhaman College of Engineering. ABSTRACT: Arithmetic logic unit (ALU) is an important part of microprocessor. In

More information

FUNDAMENTALS OF MODERN VLSI DEVICES

FUNDAMENTALS OF MODERN VLSI DEVICES 19-13- FUNDAMENTALS OF MODERN VLSI DEVICES YUAN TAUR TAK H. MING CAMBRIDGE UNIVERSITY PRESS Physical Constants and Unit Conversions List of Symbols Preface page xi xiii xxi 1 INTRODUCTION I 1.1 Evolution

More information

Device Technologies. Yau - 1

Device Technologies. Yau - 1 Device Technologies Yau - 1 Objectives After studying the material in this chapter, you will be able to: 1. Identify differences between analog and digital devices and passive and active components. Explain

More information

DESIGN AND ANALYSIS OF LOW POWER 10- TRANSISTOR FULL ADDERS USING NOVEL X-NOR GATES

DESIGN AND ANALYSIS OF LOW POWER 10- TRANSISTOR FULL ADDERS USING NOVEL X-NOR GATES DESIGN AND ANALYSIS OF LOW POWER 10- TRANSISTOR FULL ADDERS USING NOVEL X-NOR GATES Basil George 200831005 Nikhil Soni 200830014 Abstract Full adders are important components in applications such as digital

More information

CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON

CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Instructor: Andy Phelps TAs: Newsha Ardalani, Peter Ohmann, and Jai Menon Midterm Examination 2 In Class (50 minutes) Wednesday,

More information

ECE 410: VLSI Design Course Lecture Notes (Uyemura textbook)

ECE 410: VLSI Design Course Lecture Notes (Uyemura textbook) ECE 410: VLSI Design Course Lecture Notes (Uyemura tetbook) Professor Fathi Salem Michigan State University We will be updating the notes this Semester. Lecture Notes Page 2.1 Electronics Revolution Age

More information

Chapter 2 : Semiconductor Materials & Devices (II) Feb

Chapter 2 : Semiconductor Materials & Devices (II) Feb Chapter 2 : Semiconductor Materials & Devices (II) 1 Reference 1. SemiconductorManufacturing Technology: Michael Quirk and Julian Serda (2001) 3. Microelectronic Circuits (5/e): Sedra & Smith (2004) 4.

More information

12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders

12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders 12-nm Novel Topologies of LPHP: Low-Power High- Performance 2 4 and 4 16 Mixed-Logic Line Decoders Mr.Devanaboina Ramu, M.tech Dept. of Electronics and Communication Engineering Sri Vasavi Institute of

More information

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press

UNIT-1 Bipolar Junction Transistors. Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press UNIT-1 Bipolar Junction Transistors Text Book:, Microelectronic Circuits 6 ed., by Sedra and Smith, Oxford Press Figure 6.1 A simplified structure of the npn transistor. Microelectronic Circuits, Sixth

More information

Digital Electronics Part II - Circuits

Digital Electronics Part II - Circuits Digital Electronics Part II - Circuits Dr. I. J. Wassell Gates from Transistors 1 Introduction Logic circuits are non-linear, consequently we will introduce a graphical technique for analysing such circuits

More information

Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique

Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique Low Power 8-Bit ALU Design Using Full Adder and Multiplexer Based on GDI Technique Mohd Shahid M.Tech Student Al-Habeeb College of Engineering and Technology. Abstract Arithmetic logic unit (ALU) is an

More information

Logic Design (Part 1) Transistors & Gates (Chapter 3)

Logic Design (Part 1) Transistors & Gates (Chapter 3) Agenda next 3 weeks: Inside a microprocessor Logic Design (Part 1) Transistors & Gates (Chapter 3) Based on slides McGrawHill Additional material 2004/2005/2006 Lewis/Martin Additional material 2008 Roth

More information

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,

More information

Topic 2. Basic MOS theory & SPICE simulation

Topic 2. Basic MOS theory & SPICE simulation Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris, Ch 2 & 5.1-5.3 Rabaey, Ch 3) URL: www.ee.ic.ac.uk/pcheung/

More information

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor

Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,

More information

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 Paper Setter Detail Name Designation Mobile No. E-mail ID Raina Modak Assistant Professor 6290025725 raina.modak@tib.edu.in

More information

Gates and Circuits 1

Gates and Circuits 1 1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior

More information

Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders

Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders Design of Low-Power High-Performance 2-4 and 4-16 Mixed-Logic Line Decoders B. Madhuri Dr.R. Prabhakar, M.Tech, Ph.D. bmadhusingh16@gmail.com rpr612@gmail.com M.Tech (VLSI&Embedded System Design) Vice

More information

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates 18.1 18.2 Spiral 1 / Unit 8 Transistor Implementations MOS Logic Gates Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand

More information

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations

EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies. Overview of Physical Implementations EECS150 - Digital Design Lecture 15 - CMOS Implementation Technologies Mar 12, 2013 John Wawrzynek Spring 2013 EECS150 - Lec15-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

BICMOS Technology and Fabrication

BICMOS Technology and Fabrication 12-1 BICMOS Technology and Fabrication 12-2 Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with

More information

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. ! ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Lecture Outline! Review: MOS IV Curves and Switch Model! MOS Device Layout!

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 3: January 21, 2016 MOS Fabrication pt. 2: Design Rules and Layout Penn ESE 570 Spring 2016 Khanna Adapted from GATech ESE3060 Slides Lecture

More information

Lecture #29. Moore s Law

Lecture #29. Moore s Law Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday

More information

A SUBSTRATE BIASED FULL ADDER CIRCUIT

A SUBSTRATE BIASED FULL ADDER CIRCUIT International Journal on Intelligent Electronic System, Vol. 8 No.. July 4 9 A SUBSTRATE BIASED FULL ADDER CIRCUIT Abstract Saravanakumar C., Senthilmurugan S.,, Department of ECE, Valliammai Engineering

More information

VLSI Designed Low Power Based DPDT Switch

VLSI Designed Low Power Based DPDT Switch International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 8, Number 1 (2015), pp. 81-86 International Research Publication House http://www.irphouse.com VLSI Designed Low

More information

Lecture 8. MOS Transistors; Cheap Computers; Everycircuit

Lecture 8. MOS Transistors; Cheap Computers; Everycircuit Lecture 8 MOS Transistors; Cheap Computers; Everycircuit Copyright 2017 by Mark Horowitz 1 Reading The rest of Chapter 4 in the reader For more details look at A&L 5.1 Digital Signals (goes in much more

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

Sticks Diagram & Layout. Part II

Sticks Diagram & Layout. Part II Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped

More information

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important!

Homework 10 posted just for practice. Office hours next week, schedule TBD. HKN review today. Your feedback is important! EE141 Fall 2005 Lecture 26 Memory (Cont.) Perspectives Administrative Stuff Homework 10 posted just for practice No need to turn in Office hours next week, schedule TBD. HKN review today. Your feedback

More information

Implementation of Full Adder using Cmos Logic

Implementation of Full Adder using Cmos Logic ISSN: 232-9653; IC Value: 45.98; SJ Impact Factor:6.887 Volume 5 Issue VIII, July 27- Available at www.ijraset.com Implementation of Full Adder using Cmos Logic Ravika Gupta Undergraduate Student, Dept

More information

Gates and and Circuits

Gates and and Circuits Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the

More information

Lab# 13: Introduction to the Digital Logic

Lab# 13: Introduction to the Digital Logic Lab# 13: Introduction to the Digital Logic Revision: October 30, 2007 Print Name: Section: In this lab you will become familiar with Physical and Logical Truth tables. As well as asserted high, asserted

More information

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true

More information

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1

1 FUNDAMENTAL CONCEPTS What is Noise Coupling 1 Contents 1 FUNDAMENTAL CONCEPTS 1 1.1 What is Noise Coupling 1 1.2 Resistance 3 1.2.1 Resistivity and Resistance 3 1.2.2 Wire Resistance 4 1.2.3 Sheet Resistance 5 1.2.4 Skin Effect 6 1.2.5 Resistance

More information

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies

EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies EECS150 - Digital Design Lecture 9 - CMOS Implementation Technologies Feb 14, 2012 John Wawrzynek Spring 2012 EECS150 - Lec09-CMOS Page 1 Overview of Physical Implementations Integrated Circuits (ICs)

More information

A HIGH SPEED & LOW POWER 16T 1-BIT FULL ADDER CIRCUIT DESIGN BY USING MTCMOS TECHNIQUE IN 45nm TECHNOLOGY

A HIGH SPEED & LOW POWER 16T 1-BIT FULL ADDER CIRCUIT DESIGN BY USING MTCMOS TECHNIQUE IN 45nm TECHNOLOGY A HIGH SPEED & LOW POWER 16T 1-BIT FULL ADDER CIRCUIT DESIGN BY USING MTCMOS TECHNIQUE IN 45nm TECHNOLOGY Jasbir kaur 1, Neeraj Singla 2 1 Assistant Professor, 2 PG Scholar Electronics and Communication

More information

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407 Index A Accuracy active resistor structures, 46, 323, 328, 329, 341, 344, 360 computational circuits, 171 differential amplifiers, 30, 31 exponential circuits, 285, 291, 292 multifunctional structures,

More information

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1

Lecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation

More information

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

More information

nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect

nmos, pmos - Enhancement and depletion MOSFET, threshold voltage, body effect COURSE DELIVERY PLAN - THEORY Page! 1 of! 7 Department of Electronics and Communication Engineering B.E/B.Tech/M.E/M.Tech : EC Regulation: 2016(Autonomous) PG Specialization : Not Applicable Sub. Code

More information

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET

Depletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage

More information

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag PHYSICAL STRUCTURE OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Integrated Circuit Layers MOSFETs CMOS Layers Designing FET Arrays EE 432 VLSI Modeling and Design 2 Integrated Circuit Layers

More information

UNIT-II LOW POWER VLSI DESIGN APPROACHES

UNIT-II LOW POWER VLSI DESIGN APPROACHES UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.

More information

Solid State Devices- Part- II. Module- IV

Solid State Devices- Part- II. Module- IV Solid State Devices- Part- II Module- IV MOS Capacitor Two terminal MOS device MOS = Metal- Oxide- Semiconductor MOS capacitor - the heart of the MOSFET The MOS capacitor is used to induce charge at the

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

Introduction to deep-submicron CMOS circuit design

Introduction to deep-submicron CMOS circuit design National Institute of Applied Sciences Department of Electrical & Computer Engineering Introduction to deep-submicron CMOS circuit design Etienne Sicard http:\\intrage.insa-tlse.fr\~etienne 1 08/09/00

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 MOS Transistor Theory Study conducting channel between

More information

IFSIN. WEB PAGE Fall ://weble.upc.es/ifsin/

IFSIN. WEB PAGE   Fall ://weble.upc.es/ifsin/ IFSIN IMPLEMENTACIÓ FÍSICA DE SISTEMES INTEGRATS NANOMÈTRICS IMPLEMENTACIÓN N FÍSICA F DE SISTEMAS INTEGRADOS NANOMÉTRICOS PHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS Fall 2008 Prof. Xavier

More information

Lecture Integrated circuits era

Lecture Integrated circuits era Lecture 1 1.1 Integrated circuits era Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell laboratories. In 1961, first IC was introduced. Levels of Integration:-

More information

Lab Report: Digital Logic

Lab Report: Digital Logic Lab Report: Digital Logic Introduction The aim of the Digital Logic Lab was to construct a simple 4-bit Arithmetic Logic Unit (ALU) in order to demonstrate methods of using Boolean Algebra to manipulate

More information

A Low Power and Area Efficient Full Adder Design Using GDI Multiplexer

A Low Power and Area Efficient Full Adder Design Using GDI Multiplexer A Low Power and Area Efficient Full Adder Design Using GDI Multiplexer G.Bramhini M.Tech (VLSI), Vidya Jyothi Institute of Technology. G.Ravi Kumar, M.Tech Assistant Professor, Vidya Jyothi Institute of

More information

Lecture 2: Digital Logic Basis

Lecture 2: Digital Logic Basis Lecture 2: Digital Logic Basis Xufeng Kou School of Information Science and Technology ShanghaiTech University 1 Outline Truth Table Basic Logic Operation and Gates Logic Circuits NOR Gates and NAND Gates

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple

More information

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline

EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies. Recap and Outline EECS150 - Digital Design Lecture 19 CMOS Implementation Technologies Oct. 31, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information