Lecture 0: Introduction
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1 Introduction to CMOS VLSI Design Lecture : Introduction David Harris Steven Levitan Harvey Mudd College University of Pittsburgh Spring 24 Fall 28
2 Administrivia Professor Steven Levitan TA: Bo Zhao Syllabus Approximate subject to change Office Hours & Lab Assistant Hours Labs, Exams, and Project Grading Collaboration, yes Cheating, No Textbook: Harris and Weste Other refrerences on line and on reserve in Library Several Fundamental Ideas and many many many details - take good notes : Introduction CMOS VLSI Design Slide 2 2
3 Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Complementary Metal Oxide Semiconductor Fast, cheap, low power transistors Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip : Introduction CMOS VLSI Design Slide 3 3
4 Deconstructing a Computer System : Introduction 4 Steven Levitan 9 Nov
5 Deconstructing a Computer System : Introduction 5 clean dell computer.jpg Steven Levitan 9 Nov
6 Deconstructing a Computer System : Introduction 6 Steven Levitan 9 Nov
7 Deconstructing a Computer System : Introduction 7 Board_6.jpg Steven Levitan 9 Nov
8 Deconstructing a Computer System : Introduction 8 Steven Levitan 9 Nov
9 From Chips to DIPs Single die Slicing and Dicing Wafer : Introduction 9 From Steven Levitan 9 Nov
10 Going Back and Zooming In Quad Core Barcelona 27 : Introduction Steven Levitan 9 Nov 27
11 Going Back and Zooming In 22 22M Transistors 42mm 2 : Introduction Steven Levitan 9 Nov 27
12 Going Back and Zooming In 998 Pentium(II) 7.5M Transistors 8mm 2 : Introduction 2 Steven Levitan 9 Nov
13 Going Back and Zooming In K Transistors mm 2 : Introduction 3 Steven Levitan 9 Nov
14 Going Back and Zooming In 97 2K Transistor 44 2mm 2 : Introduction 4 Steven Levitan 9 Nov
15 Going Back and Zooming In ECL 3 input Gate Motorola 966 : Introduction 5 Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed Steven Levitan 9 Nov
16 Photomasks to Circuits Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed : Introduction 6 Weste & Harris CMOS VLSI Design Copyright 25 Pearson Addison-Wesley. All rights reserved. Steven Levitan 9 Nov
17 The Y Abstraction Spiral Start Here End Here Gajski & Kuhn : Introduction 7 Steven Levitan 9 Nov
18 MOS Technology GATE.6 um um Rabaey, Chandrakasan, Nikolic Digital Integrated Circuits2nd ed : Introduction 8 Steven Levitan 9 Nov
19 Patterned Materials Create Circuits Silicon Crystal N type Doping P type Doping : Introduction 9 Weste & Harris CMOS VLSI Design Copyright 25 Pearson Addison-Wesley. All rights reserved. Steven Levitan 9 Nov
20 Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si : Introduction CMOS VLSI Design Slide 2 2
21 Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) Si Si - Si Si Si + Si Si + As Si Si B - Si Si Si Si Si Si Si : Introduction CMOS VLSI Design Slide 2 2
22 p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode : Introduction CMOS VLSI Design Slide 22 22
23 nmos Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal Source Gate Drain Polysilicon SiO 2 n+ n+ p bulk Si : Introduction CMOS VLSI Design Slide 23 23
24 nmos Operation Body is commonly tied to ground ( V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S D : Introduction CMOS VLSI Design Slide 24 24
25 nmos Operation Cont. When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON Source Gate Drain Polysilicon SiO 2 n+ p n+ bulk Si S D : Introduction CMOS VLSI Design Slide 25 25
26 pmos Transistor Similar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior Source Gate Drain Polysilicon SiO 2 p+ p+ n bulk Si : Introduction CMOS VLSI Design Slide 26 26
27 Power Supply Voltage GND = V In 98 s, V DD = 5V V DD has decreased in modern processes High V DD would damage modern tiny transistors Lower V DD saves power V DD = 3.3, 2.5,.8,.5,.2,., : Introduction CMOS VLSI Design Slide 27 27
28 Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g = g = nmos g d d OFF d ON s s s d d d pmos g ON OFF s s s : Introduction CMOS VLSI Design Slide 28 28
29 Transistors as Switches Input voltage on the CMOS N Switch gate controls the current through the source/drain path D G S N Switch D This provides output voltage to drive next circuit. G S Series / Parallel paths provide and and or logic functions G D S D S G : Introduction 29 Steven Levitan 9 Nov
30 From Switches to Boolean Functions... Use the switching functions to provide paths to Vdd or GND Vdd is the source of all Truth (Vdd = = ) GND is the source of all Falsehood (GND == ) P-channel N-channel : Introduction 3 Steven Levitan 9 Nov
31 The Inverter True to False / False to True Converter / / : Introduction 3 Steven Levitan 9 Nov
32 CMOS Inverter A Y V DD A Y A Y GND : Introduction CMOS VLSI Design Slide 32 32
33 CMOS Inverter A A Y Y V DD OFF A= Y= ON GND : Introduction CMOS VLSI Design Slide 33 33
34 CMOS Inverter A A Y Y V DD ON A= Y= OFF GND : Introduction CMOS VLSI Design Slide 34 34
35 Series/Parallel Circuits => Logic +Vdd CMOS NAND (not AND) Gate A B Y Truth Table A B Y Y = A B = A + B : Introduction 35 Steven Levitan 9 Nov
36 CMOS NAND Gate A B Y A B Y : Introduction CMOS VLSI Design Slide 36 36
37 CMOS NAND Gate A B Y A= ON ON Y= OFF B= OFF : Introduction CMOS VLSI Design Slide 37 37
38 CMOS NAND Gate A B Y A= OFF ON Y= OFF B= ON : Introduction CMOS VLSI Design Slide 38 38
39 CMOS NAND Gate A B Y A= ON OFF Y= ON B= OFF : Introduction CMOS VLSI Design Slide 39 39
40 CMOS NAND Gate A B Y A= OFF OFF Y= ON B= ON : Introduction CMOS VLSI Design Slide 4 4
41 CMOS NOR Gate A B Y A B Y : Introduction CMOS VLSI Design Slide 4 4
42 3-input NAND Gate Y pulls low if ALL inputs are Y pulls high if ANY input is : Introduction CMOS VLSI Design Slide 42 42
43 3-input NAND Gate Y pulls low if ALL inputs are Y pulls high if ANY input is A Y B C : Introduction CMOS VLSI Design Slide 43 43
44 From Logic to Binary Math Truth tables for binary addition/subtraction etc. A B A AND Carry Sum B XOR Sum Carry Sum = A xor B Carry = A and B Are these Amino Acids? : Introduction 44 Steven Levitan 9 Nov
45 F = ^(AB + AC + BC) => Carry Cout C = A = B = + : Introduction 45 Steven Levitan 9 Nov
46 Chip Photomask Layout : Introduction 46 Steven Levitan 9 Nov
47 Latches for State Cross coupled, charge storage, etc. Save logic values, change under temporal control (clocks) Set QB Reset Q DATA N+ Inputs DATA N Outputs S R Q QB Q QB hold Illegal Are these (folded) proteins? Latch Control (Clock) : Introduction 47 Steven Levitan 9 Nov
48 Finite State Machines FSM s capture processes Input Inputs, outputs, state Out = F((in), State n ) Next State & Output Calculation Output State n+ = F(in, State n ) Like a Markov process Current State Latch S S5 S3 Is this a regulatory process? S2 If (state = ) and (input = A) then state <= 4, output <= 5 : Introduction 48 Steven Levitan 9 Nov
49 (Re) Composing : Introduction 49 Steven Levitan 9 Nov
50 Computer Micro Architecture Basic operation on triples A <= B + C; R[2] <= R[] op R[]. Data from Register File 2. Operations done by Arithmetic and Logic Unit 3. Data returned to Register File Instruction Register SRC SRC2 DEST Op CC Register File ALU Op ={add, sub, shift, and, or, etc} CC = {zero, neg, overflow, etc} : Introduction 5 Steven Levitan 9 Nov
51 Instruction Set OP Code Src Src2 Destination Op Code Memory Address Three (four) types of instructions:. Move Data to / from Memory locations, I/O and temporary registers 2. Compute Logical, fixed point, floating point, string, bits 3. Program Flow Branch, Jump, Subroutines 4. Mode Control Privileged modes, interrupts, memory mapping Four addresses (explicit/implicit) Source, Source2, Destination, Next (PC) B+C => A (and do next instruction) Instruction set and micro-architecture define the complete computing system : Introduction 5 Steven Levitan 9 Nov
52 von Neumann Architecture I/O CPU Control PC Accumulator IR Fetch/Execute Cycle MAR < PC MBR < MEM[MAR] Increment PC IR < MBR Interpret instruction in IR MAR MBR (now called 5 stage pipeline ) Memory Done as a FSM in Control Unit Is this just like EIS.. Is this a ribosome? : Introduction 52 Steven Levitan 9 Nov
53 Summary MOS Transistors are stack of gate, oxide, silicon Can be viewed as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip! : Introduction CMOS VLSI Design Slide 53 53
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