Sticks Diagram & Layout. Part II

Transcription

1 Sticks Diagram & Layout Part II

2 Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate (body) contacts / taps GND Y V DD p+ n+ n+ p+ p+ n+ p substrate n well substrate tap well tap

3 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line Y GND V DD substrate tap nmos transistor pmos transistor well tap

4 Inverter GND Y V DD V DD M 2 In Out p+ n+ n+ p+ p+ n+ p substrate n well M 1 substrate tap well tap V DD Y Out GND V DD substrate tap nmos transistor pmos transistor well tap GND In

5 CMOS Inverter Layout GND In V DD Out (a) Layout

6 Transistor layout n-type (tubs may vary): L w

7 Example: Inverter

8 Example: NND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 λ by 40 λ

9 Example: O3I Sketch a stick diagram for O3I and estimate area Y = ( + B+ C) D

10 Wires and Vias Creating wires (review): Deposit insulator on chip (SiO 2 ) Deposit conducting material on chip Selectively remove using photolithography Use multiple layers so wires can cross over each other Vias (Contacts) - Connect between layers cuts etched through insulator Metal connects between layers (with significant resistance) Wafer

11 Wires and vias metal 3 metal 2 metal 1 vias poly poly n+ p-tub n+

12 Example Problems - Parasitic Calculation (1/10) metal1 30λ 1λ=0.25µm poly ndiff Rmetal1=? Cmetal1=? Rpoly=? Cpoly=? Rndiff=? Cndiff=? Note: see Table 2-4, p. 80 for parameters

13 Example Problems - Parasitic Calculation (6/10) 1λ=0.25µm What are the parasitic capacitances visible from point? Cpoly Cgate Coverhang

14 Stick diagrams (1/3) stick diagram is a cartoon of a layout. Does show all components/vias (except possibly tub ties), relative placement. Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.

15 Stick Diagrams (2/3) Key idea: "Stick figure cartoon" of a layout Useful for planning layout relative placement of transistors assignment of signals to layers connections between cells cell hierarchy

16 Stick Diagrams (3/3) Layers Metal (BLUE) Polysilicion (RED ) N-Diffusion (Green) P-Diffusion (Brown) Contact / Via Connection Rules poly n-diff p-diff metal poly S N P NC n-diff S X NC p-diff metal S NC S

17 Example - Stick Diagrams (1/2) B lternatives - Pull-up Network B Circuit Diagram. Pull-Down Network (The easy part!) Complete Stick Diagram

18 Example - Stick Diagrams (2/2) In Out B Out Gnd Gnd Inverter NND Gate

19 Dynamic latch stick diagram VDD in out VSS phi phi

20 Stick Diagram XOR Gate Examples B B B B Out B B B B Out B Gnd B Exclusive OR Gate

21 Hierarchical Stick Diagrams Define cells by outlines & use in a hierarchy to build more complex cells B Out B NND Out Gnd Gnd Gnd Gnd NND Cell Stick Diagram NND Cell Outline

22 Cell Connection Schemes External connection - wire cells together butment - design cells to connect when adjacent Reflection, mirroring - use to make abutment possible

23 Example: 2-input multiplexer First cut: S B S OUT = *S + B*S OUT S B S Gnd Out NND B Gnd Gnd Out NND B Gnd Gnd Out NND B Gnd Gnd Out

24 Sticks design of multiplexer Start with NND gate: + out b a

25 NND sticks VDD a out b VSS

26 Refined one-bit Mux Design Use NND cell as black box rrange easy power connections Vertical connections for allow multiple bits select select B Gnd Out NND B Gnd Gnd Out NND B Gnd Gnd Out NND B Gnd Gnd Out

27 3-bit mux sticks select select VDD a a 2 i m2(one-bit-mux) o i o 2 VSS b 2 select select b i a 1 b 1 a i b i select select VDD m2(one-bit-mux) o i VSS o1 a 0 b 0 a i b i select select VDD m2(one-bit-mux) o i VSS o0

28 Multiple-Bit Mux select select NND B Gnd Gnd Out NND B Gnd Gnd Out NND B Gnd Gnd Out 0 0 Gnd Out0 NND B Gnd Gnd Out NND B Gnd Gnd Out NND B Gnd Gnd Out 1 B1 Gnd Out1

29 Cell Mirroring, Overlap Use mirroring, overlap to save area 0 B0 Gnd NND B Gnd Out Gnd NND B Gnd Out Gnd NND B Gnd Out Gnd B1 1

30 Example: Layout / Stick Diagram Create a layout for a NND gate given constraints: Use minimum-size transistors ssume power supply lines pass through cell from left to right at top and bottom of cell ssume inputs are on left side of cell ssume output is on right side of cell Optimize cell to minimize width Optimize cell to minimize overall area

31 Layout Example!! B OUT B B Gnd! Gnd! Circuit Diagram. Exterior of Cell

32 Example - Magic Layout Overall Layout: 52 X 16

33 Review - VLSI Levels of bstraction Specification (what the chip does, inputs/outputs) rchitecture major resources, connections Register-Transfer logic blocks, FSMs, connections Logic gates, flip-flops, latches, connections Circuit transistors, parasitics, connections You are Here Layout mask layers, polygons

34 Levels of bstraction - Perspective Right now, we re focusing on the low level : Circuit level - transistors, wires, parasitics Layout level - mask objects We ll work upward to higher levels: Logic level - individual gates, latches, flipflops Register- transfer level - Verilog HDL Behavior level - Specifications

35 The Challenge of Design Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints Design time - how long did it take to ship a product? Performance - how fast is the clock? Cost - NRE + unit cost CD tools - essential in modern design

36 CD Tool Survey: Layout Layout Editors Design Design Rule Checkers (DRC) Circuit Extractors Layout vs. Schematic (LVS) Comparators utomatic Layout Tools Layout Generators SIC: Place/Route for Standard Cells, Gate rrays

37 Layout Editors Goal: produce mask patterns for fabrication Grid type: bsolute grid (MX, LSI, LEdit, Mentor ICStation, other commercial tools) Magic: lambda-based grid - easier to learn, but less powerful Mask description: bsolute mask (one layer for each mask) Magic: symbolic masks (layers combine to generate actual mask patterns)

38 Design Rule Checkers Goal: identify design rule violations Often a separate tool (built in to Magic) General approach: scanline algorithm Computationally intensive, especially for large chips

39 Circuit Extractors Goal: extract netlist of equivalent circuit Identify active components Identify parasitic components Capacitors Resistors

40 Layout Versus Schematic (LVS) Goal: Compare layout, schematic netlists Compare transistors, connections (ignore parasitics) Issue error if two netlists are not equivalent Important for large designs

41 Design Rules Have to be respected when a given design is laid out. Represent the physical limits of the manufacturing process. Width, spacing, overlap, surround, extension. detailed and up-to-date sets of design rules.

42 Design Rules Checker, DRC Is a program. Checks that all polygons and layers from the layout database meet all of the manufacturing process rules, i.e. no violation of the design rules. Checks for minimum spacing and minimum size, and ensures that combinations of layers form legal components.

43 DRC Pass Indicates that: The design can be fabricated within the limitations of the manufacturing process. The device fabricated can function.

44 What happens if You ignore the DRC violations indicated to you? You use bigger dimensions than the minimum stated by the Design Rules?

45 ssignment Read all the chapters we have covered. Do all the related questions in the textbook. What is GDSII and CIF?

46 For Lab Print out the DRC rules and take it along with you to lab. Make sure you pass the DRC and LVS!!

47 LVS, ERC, LPE, Tape-Out and Chapter 3 Tuesday, Jan. 20th

48 Review MOSIS TSMC

49 Layout Verification Tools DRC LVS ERC LPE

50 DRC What can you recall?

51 LVS Layout Versus Schematic. nother CD tool in the design environment.

52 LVS To check that the design is connected correctly. The schematic = Reference circuit. Either logic or electronic schematic. The layout is checked against the schematic.

53 What is checked in LVS? Electrical connectivity of all signals. Input Output Power signals. Device sizes. Transistor width and length. Resistor sizes. Capacitor sizes.

54 What is checked in LVS? Identification of extra components and signals that have not been included in the schematic. Floating nodes.

55 ERC, Electrical Rules Check subset of the LVS check. Useful to accelerate debugging, e.g. V DD to V SS short-circuit.

56 ERC The electrical rules checked are limited to errors in connectivity or device connection, e.g. Unconnected, or partly connected, or extra devices. Disabled transistors. Floating nodes. Short circuits. Special checks.

57 GDSII Data transfer issue. binary database format that enables data to be exchanged within different ED/CD tools, e.g. export data from Mentor to Cadence. Developed by Calma on Data General machines. Other alternatives: CIF, LEF, DEF

58 GDSII Mask shop requires GDSII file type. Database is translated from the design layers that were used and verified into the mask shop layers. Then, verified as the final golden verification. few structures are added for the processing needs; that won t pass DRC or LVS verfications.

59 LPE Layout Parasitic Extraction

60 Tape-out Procedures To generate a tape for PG. The GDSII files are transferred to the fabrication group on a magnetic tape. Steps discussed, as well as specific documentations and release procedures.