EE 330 Lecture 5. Improved Device Models Propagation Delay in Logic Circuits

Transcription

1 EE 330 Lecture 5 Improved evice Models Propagation elay in Logic Circuits

2 Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation rain rain ulk Cross-ectional View n-channel MOFET n-type n+-type Top View rain p-type p+-type io 2 (insulator) POL (conductor) esigner always works with top view Complete ymmetry in construction between rain and

3 Review from Last Time MO Transistor Comparison of Operation rain rain G = 0 G = 1 G = 0 G = 1 assumed connected to (or close to) ground assumed connected to (or close to) V and oolean G at gate is relative to ground

4 Review from Last Time Pull-up and Pull-down Networks Three key characteristics of tatic CMO s 1. PU network comprised of p-channel devices 2. P network comprised of n-channel devices 3. One and only one of these networks is conducting at the same time Three properties of tatic CMO s (based upon simple switch-level model) 1. V H =V, V L =0 (too good to be true?) X n V PUN PN 2. P H =P L =0 (too good to be true?) 3. t HL =t LH =0 (too good to be true?) These 3 properties are inherent in oolean circuits with these 3 characteristics

5 Example 1: Circuit tructures Circuit esign How many transistors are required to realize the function F C in a basic CMO process if static NN and NOR gates are used? ssume, and C are available.

6 Example 1: How many transistors are required to realize the function F C in a basic CMO process if static NN and NOR gates are used? ssume, and C are available. olution: C F 20 transistors and 5 levels of logic

7 How many transistors are required to realize the function in a basic CMO process if static NN and NOR gates are used? ssume, and C are available. C F olution (alternative): From basic oolean Manipulations C C F C 1 F F 8 transistors and 3 levels of logic Example 1:

8 Example 1: How many transistors are required to realize the function F C in a basic CMO process if static NN and NOR gates are used? ssume, and C are available. olution (alternative): From basic oolean Manipulations F 1 C F F 6 transistors and 2 levels of logic

9 Example 2: XOR Function = widely-used 2-input tatic CMO implementation = + 22 transistors 5 levels of logic elays unacceptable (will show later) and device count is too large!

10 Example 3: C tandard tatic CMO Implementation C 3 levels of Logic 16 Transistors if asic CMO s are Used Can the same oolean functionality be obtained with less transistors?

11 Observe: V C C C ignificant reduction in transistor count and levels of logic for realizing same oolean function Termed a Complex Logic implementation ome authors term this a compound gate

12 Complex Logic s Pull-up Network C V Pull-down Network C C

13 Complex s V Pull up and pull down network never both conducting One of the two networks is always conducting C C

14 Complex s Nomenclature: V PUN X n PN When the logic gate shown is not a multiple-input NN or NOR gate but has Characteristics 1, 2, and 3 above, the gate will be referred to as a Complex Logic Complex Logic s also implement static logic functions and some authors would refer to this as tatic CMO Logic as well but we will make the distinction and refer to this as Complex Logic s

15 Complex s V PUN X n PN Complex esign trategy: 1. Implement in the PN 2. Implement in the PUN (must complement the input variables since p- channel devices are used) ( and often expressed in either OP or PO form)

16 XOR in Complex Logic s = Will express and in standard OP or PO form

17 XOR in Complex Logic s = = + = + = = + +

18 XOR in Complex Logic s = + = + + PN PUN

19 XOR in Complex Logic s V = + = transistors and 2 levels of logic Notice a significant reduction in the number of transistors required

20 XOR in Complex Logic s = + = + + Multiple PU and P networks can be used =

21 Complex Logic ummary: V PUN X n PN If PUN and PN satisfy the characteristics: 1. PU network comprised of p-channel device 2. P network comprised of n-channel device 3. One and only one of these networks is conducting at the same time Properties of PU/P logic of this type (with simple switch-level model): Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model)

22 Consider tandard CMO Implementation 2 levels of Logic 6 Transistors if asic CMO s are Used asic noninverting functions generally require more complexity if basic CMO gates are used for implementation

23 Pass Transistor Logic V R Requires only 2 transistors rather than 6 for a standard CMO gate (and a resistor).

24 Pass Transistor Logic R Even simpler pass transistor logic implementations are possible Requires only 1 transistor (and a resistor). Will see later that the area of a single practical resistor for this circuit may be comparable to that needed for hundreds or even thousands of transistors

25 Pass Transistor Logic R May be able to replace resistor with transistor ut high logic level can not be determined with existing device model (or even low logic level for circuit on right)

26 Pass Transistor Logic R 6 transistors, 1 resistor, two levels of logic (the 4 transistors in the two inverters are not shown)

27 Pass Transistor Logic R R 2 transistors, 1 resistor, one level of logic

28 Pass Transistor Logic R Requires only 1 transistor (and a resistor) - Pass transistor logic can offer significant reductions in complexity for some functions (particularly noninverting) - Resistor may require more area than several hundred or even several thousand transistors - ignal levels may not go to V or to 0V - tatic power dissipation may not be zero - ignals may degrade unacceptably if multiple gates are cascaded - resistor often implemented with a transistor to reduce area but signal swing and power dissipation problems still persist - Pass transistor logic is widely used

29 Logic esign tyles everal different logic design styles are often used throughout a given design (3 considered thus far) tatic CMO Complex Logic s Pass Transistor Logic The designer has complete control over what is placed on silicon and governed only by cost and performance New logic design strategies have been proposed recently and others will likely emerge in the future The digital designer needs to be familiar with the benefits and limitations of varying logic styles to come up with a good solution for given system requirements

30 rain MOFET Modeling rain imple model of MOFET was developed (termed switch-level model) imple gates designed in CMO Process were introduced ome have zero power dissipation ome have or appeared to have rail to rail logic voltage swings ll appeared to be Infinitely fast Logic levels of some can not be predicted with simple model imple model is not sufficiently accurate to provide insight relating to some of these properties MOFET modeling strategy hierarchical model structure will be developed generally use simplest model that can be justified

31 MO Transistor Models 1, witch-level model rain rain G = 0 G = 1 G = 0 G = 1 dvantages: imple, does not require understanding of semiconductor properties, does not depend upon process, adequate for understanding basic operation of many digital circuits Limitations: oes not provide timing information (surfaced when looking at static CMO circuits, and several others that have not yet become apparent from the applications that have been considered) and can not support design of resistor used in Pass Transistor Logic

32 Improved evice Models With the simple switch-level model, it was observed that basic static CMO logic gates have the following three properties: evice Models and Operation Rail to rail logic swings Zero static power dissipation in both =1 and =0 states rbitrarily fast (too good to be true? will consider again with better model) It can be shown that the first two properties are nearly satisfied in actual fabricated circuits but though the circuits are fast, they are observably not arbitrarily fast Will now extend switch-level model to predict speed of basic gates

33 Recall MO Transistor Qualitative iscussion of n-channel Operation ulk rain rain n-channel MOFET G = 0 G = 1

34 MO Transistor Qualitative iscussion of n-channel Operation ulk rain rain G n-channel MOFET G = 0 G = 1

35 MO Transistor Qualitative iscussion of n-channel Operation rain ulk Insulator rain For V G small n-channel MOFET ulk rain ulk Insulator Resistor For V G large n-channel MOFET

36 MO Transistor Qualitative iscussion of n-channel Operation ulk rain Insulator rain For V G small n-channel MOFET rain ulk ulk Insulator For V G large n-channel MOFET Capacitance from gate to channel region is distributed Lumped capacitance much easier to work with

37 Improved witch-level Model rain G C G R W V G witch closed for V G = 1 witch-level model including gate capacitance and channel resistance till neglect bulk connection and connect the gate capacitance to the source

38 Improved witch-level Model rain G = 1 G = 0 n-channel witch-level model G C G R W V G witch closed for V G = 1 witch-level model including gate capacitance and channel resistance

39 Improved witch-level Model rain G = 0 G =1 G p-channel witch-level model C G R W V G witch closed for V G = 0 witch-level model including gate capacitance and channel resistance

40 Improved witch-level Model rain G R W C G V G witch closed for V G = 1 witch-level model including gate capacitance and channel resistance C G and R W dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C G 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C G and R W

41 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf.01uf rea allocations shown to relative scale:

42 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf 10fF 1fF.01uf 1pf rea allocations shown to relative scale: Not enough information at this point to determine whether this very small capacitance can be neglected Will answer this important question later

43 rain Model ummary 1, witch-level model G = 1 G = 0 2, Improved switch-level model G C G R W V G witch closed for V G = large witch open for V G = small Other models will be developed later

44 End of Lecture 5