Outline. EECS Components and Design Techniques for Digital Systems. Lec 12 - Timing. General Model of Synchronous Circuit

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1 Outline EES 5 - omponents and esign Techniques for igital Systems Lec 2 - Timing avid uller Electrical Engineering and omputer Sciences University of alifornia, erkeley Performance Limits of Synchronous Systems elay in logic gates elay in wires elay in combinational networks lock Skew elay in flip-flops Glitches Lec2 EES5 a Lec2 EES5 a7 2 Recall: General Model of Synchronous ircuit General Model of Synchronous ircuit clock clock option feedback ll wires, except clock, may be multiple bits wide. Registers () collections of flip-flops clock distributed to all flip-flops typical rate? ombinational Logic locks () no internal state only a function of s Particular s/s are optional Optional eedback Lec2 EES5 a7 3 option feedback How do we measure performance? operations/sec? cycles/sec? What limits the clock rate? What happens as we increase the clock rate? Lec2 EES5 a7 4

ssuming perfect clock distribution (all flip-flops see the clock at the same time): Example: Parallel-Serial onverter T time( Q) + time(mux) + time(setup) T τ Q + τ mux + τ setup a b -4-27 Lec2 EES5

2 Limitations on lock Rate Logic Gate elay What are typical delay values? t 2 elays in flip-flops oth times contribute to limiting the clock period. ll signals must be ready and setup before rising edge of clock Lec2 EES5 a7 5 Q setup time clock to Q delay What must happen in one clock cycle for correct operation? ssuming perfect clock distribution (all flip-flops see the clock at the same time): Example: Parallel-Serial onverter T time( Q) + time(mux) + time(setup) T τ Q + τ mux + τ setup a b Lec2 EES5 a7 6 General Model of Synchronous ircuit Recall L2: Transistor-level Logic ircuits clock Inverter (NOT gate): Vdd option feedback In general, for correct operation: T time( Q) + time() + time(setup) T τ Q + τ + τ setup for all paths. How do we enumerate all paths? ny circuit or ister to any ister or circuit. setup time for circuit s depends on what it connects to -Q time for circuit s depends on from where it comes. what is the relationship between in and out? in volts 3 volts out Gnd Vdd Gnd Lec2 EES5 a Lec2 EES5 a7 8

3 Qualitative nalysis of Logic elay Gate Switching ehavior Improved Transistor Model: We refer to transistor "strength" as the amount of current that flows for a given Vds and Vgs. The strength is linearly proportional to the ratio of W/L Physical property Turn it on harder allows more current to flow Inverter: g s d s net pet NN gate: Lec2 EES5 a7 9 What is the effective resistance? Lec2 When EES5 does it a7 start? How quickly does it switch? larify your understanding elays in a series of gates ascaded gates: What is the and behavior of a NOR gate? Vout Why do we need pmos and nmos devices in a pass gate? - used for tristate Vin Lec2 EES5 a Lec2 EES5 a7 2

4 Gate elay due to fan out Gate elay with a general circuit an-out: 2 an-in oes it affect the delay of the individual gate? When does the gate begin its transition? 3 The delay of a gate is proportional to its capacitance. ecause, gates #2 and 3 turn on/off at a later time. (It takes longer for the of gate # to reach the switching threshold of gates #2 and 3 as we add more capacitance.) Lec2 EES5 a7 3 What is the delay in this circuit? ritical Path: the path with the maximum delay, from any to any. In general, we include ister set-up and -to-q times in critical path calculation. Why do we care about the critical path? Lec2 EES5 a7 4 What is the delay through arbitrary combinational logic? nnouncements Reading: K& (were in 9/2 assignment) K&.6 is great protocol example We ll do several of those as we go HW 5 out today (due /2) lass survey Lab partners Lec2 EES5 a Lec2 EES5 a7 6

5 elay in lip-flops Q setup time clock to Q delay Setup time results from delay through first latch. lock to Q delay results from delay through second latch Lec2 EES5 a7 7 Wire elay t x In general, wire behave as transmission lines : signal wave-front moves close to the speed of light» ~ft/ns Time from source to destination is called the transit time. In Is most wires are short, and the transit times are relatively short compared to the clock period and can be ignored. Not so on P boards....or long wires on fast chips» usses» Global ontrol signals» lock Rule of thumb: wire must be treated as a transmission line if its length exceed λ/ Lec2 EES5 a7 8 rchitectural Level elay Wire elay ata busses datapath ontroller Even in those cases where the transmission line effect is negligible: Wires posses distributed resistance and capacitance v v2 v3 v4 Time constant associated with distributed R is proportional to the square of the wire length v v2 v3 v4 or short wires on Is, resistance is insignificant (relative to effective R of transistors), but is important. Typically around half of of gate load is in the wires. or long wires on Is: busses, clock lines, global control signal, etc. Resistance is significant, therefore distributed R effect dominates. signals are typically rebuffered to reduce delay: clock time Lec2 EES5 a Lec2 EES5 a7 2

6 Modern rule of thumb Transistors are cheap nd their local wires Wire is what counts Often pays to do extra local computation (gates) to reduce wire delay lock Skew Unequal delay in distribution of the clock signal to various parts of a circuit: if not accounted for, can lead to erroneous behavior. (see next) omes about because:» clock wires have delay,» circuit is designed with a different number of clock buffers from the clock source to the various clock loads, or» buffers have unequal delay. ll synchronous circuits experience some clock skew:» more of an issue for high-performance designs operating with very little extra time per clock cycle. clock skew, delay in distribution Lec2 EES5 a Lec2 EES5 a7 22 lock Skew onstraints K K K K clock skew, delay in distribution If clock period T = T +T setup +T Q, circuit will fail elay relative to K = T skew + T +T setup +T Q Therefore:. ontrol clock skew a) areful clock distribution. Equalize path delay from clock source to all clock loads by controlling wires delay and buffer delay. b) don t gate clocks. 2. T T +T setup +T Q + worst case skew. Most modern large high-performance chips (microprocessors) control end to end clock skew to a few tenths of a nanosecond Lec2 EES5 a7 23 Hacking lock Skew K K K K clock skew, delay in distribution Note reversed buffer. In this case, clock skew actually provides extra time (adds to the effective clock period). This effect has been used to help run circuits as higher clock rates. Risky business! What happens when at end of distribution tree feeds back to earlier? Lec2 EES5 a7 24

7 Time to ask clarifying questions Other effects of elays on ombinational Logic Lec2 EES5 a Lec2 EES5 a7 26 Time ehavior of ombinational Networks Waveforms Visualization of values carried on signal wires over time Useful in explaining sequences of events (changes in value) Simulation tools are used to create these waveforms Input to the simulator includes gates and their connections Input stimulus, that is, signal waveforms Some terms Gate delay time for change at to cause change at» Min delay typical/nominal delay max delay» areful designers design for the worst case Rise time time for to transition from low to high voltage all time time for to transition from high to low voltage Pulse width time an stays high or low between changes Lec2 EES5 a7 27 Momentary hanges in Outputs an be useful pulse shaping circuits an be a problem incorrect circuit operation (glitches/hazards) Example: pulse shaping circuit ' = delays matter in function remains high for three gate delays after is not always changes from low to high pulse 3 gate-delays wide Lec2 EES5 a7 28

8 Oscillatory ehavior Hazards/Glitches nother pulse shaping circuit close switch initially undefined nmos inverter open switch open switch resistor + Hazards/glitches: unwanted switching at the s Occur when different paths through circuit have different propagation delays» s in pulse shaping circuits we just analyzed angerous if logic causes an action while is unstable» May need to guarantee absence of glitches Usual solutions ) Wait until signals are stable (by using a clock): preferable (easiest to design when there is a clock synchronous design) 2) esign hazard-free circuits: sometimes necessary (clock not used asynchronous design) Lec2 EES5 a Lec2 EES5 a7 3 Types of Hazards Static Hazards Static -hazard Input change causes to go from to to Static -hazard INput change causes to go from to to ynamic hazards Input change causes a double change from to to to OR from to to to ue to a literal and its complement momentarily taking on the same value Thru different paths with different delays and converging May cause an that should have stayed at the same value to momentarily take on the wrong value Example: S S Lec2 EES5 a7 3 S' S' hazard static- hazard static- hazard Lec2 EES5 a7 32

9 ynamic Hazards ynamic Hazards ue to the same versions of a literal taking on opposite values Thru different paths with different delays and reconverging May cause an that was to change value to change 3 times instead of once Example: t u v t v u w hazard dynamic hazards Lec2 EES5 a7 33 w Lec2 EES5 a7 34 Eliminating Static Hazards Eliminating ynamic Hazards \ ollowing 2-level logic function has a hazard, e.g., when s change from = to G G3 \ \ G G G3 G3 \ = = G No Glitch in this case = Lec2 = EES5 ( is a7 still ) = ( is 35) This is the fix Glitch in this case G3 \ G G3 \ \ G Slow G3 \ G4 V ery slow G5 Very difficult! circuit that is static hazard free can still have dynamic hazards est approach: esign critical circuits to be two level and eliminate all static hazards OR, use good clocked synchronous design style Lec2 EES5 a7 36

Protocols Specified communication and coordination between distinct subsystems Realized by cooperating state machines Examples everywhere in digital design Rate matching us protocols» Memory,

Parallel to Serial onverter No protocol between s Every cycle they all move together elays, rates, communication all designed together.

10 Protocols Specified communication and coordination between distinct subsystems Realized by cooperating state machines Examples everywhere in digital design Rate matching us protocols» Memory, chip-to-chip, I/O, rbitration for a shared resource Serial protocols Link protocols SM Network protocols Syncronous or asynchronous Parallel or serial 2-party or multi-party SM Our old friend Parallel to Serial onverter No protocol between s Every cycle they all move together elays, rates, communication all designed together Lec2 EES5 a Lec2 EES5 a7 38 ready Simple Protocol Example Producer Register onsumer ragment of producer SM Write/ready ragment of consumer SM ~ready wait read/ ready -way communication protocol No handshake ssumes consumer is always ready to receive ready nother Protocol Example Producer Register onsumer done ragment of producer SM ~done ~ready wait done Write/ready ragment of consumer SM wait ready read/done 2-way handshake ssumes consumer is always ready to receive Lec2 EES5 a Lec2 EES5 a7 4

11 Summary ll gates have delays R delay in driving the Wires are distributed Rs elays goes with the square of the length Source circuits determines strength Serial vs parallel elays in combinational logic determine by Input delay Path length elay of each gate along the path Worst case over all possible -s Setup and K-Q determined by the two latches in flipflop lock cycle : T cycle T +T setup +T Q + worst case skew elays can introduce glitches in combinational logic Subsystems glued together via protocols elays, rates, design partitioning Lec2 EES5 a7 4

Module 4: Combinational Logic Glitches and Hazards

Module 4: Combinational Logic Glitches and Hazards Wakerly: Chapter 4 (part 3) : ECEN 3233 r. Keith. Teague Spring 23 23 TIME RESPONSE in Combinational Networks emphasis on timing behavior of circuits