Clock Signal Review Memory Elements

Size: px

Start display at page:

Download "Clock Signal Review Memory Elements"

Lucas Young
5 years ago
Views:

1 equential ystems eview ombinational etwork Output value only depends on input value equential etwork Output Value depends on input value and present state value equential network must have some way of retaining state via memory devices. Use a clock signal in a synchronous sequential system to control changes between states B /99 equential ystem iagram n k-bit Present tate Value k ombinational ogic ircuit Memory lements - flip-flop -latch - register -POM k m k-bit ext tate Value m outputs only depend on k P bits - Moore Machine MMB: Moore is ess!! m outputs depend on k P bits A n inputs - Mealy Machine lide by Prof Mitch horton B /99 2 lock ignal eview Memory lements voltage time τ - period (in seconds) f - frequency pulse width (in ertz) P w rising edge falling edge P w - pulse width (in seconds) f = /τ duty cycle - ratio of pulse width to period (in %) duty cycle = P w /τ lide by Prof Mitch horton millisecond (ms) Kilohertz (Kz) -3 3 microsecond (µs) Megahertz (Mz) -6 6 nanosecond (ns) igahertz (z) -9 9 B /99 3 Memory elements used in sequential systems are flip-flops and latches. (t+) (t+) is next state flip flop (FF) Flip-flops are edge triggered (either rising or falling edge). latch () atches are level sensitive. follows when =, latches when goes from to. B /99 4 for FF, for latch FF, atch operation J K Other tate lements J K (t+) (t) (t) JK useful for single bit flags with separate set(j), reset(k) control. input (FF) (t+) (t) (t) Useful for counter design. () B /99 5 B /99 6

2 FFs are most common Most FPA families only have FFs FF is fastest, simplest (fewest transistors) of FFs Other FF types (, JK) can be built from FFs We will use FFs almost exclusively in this class Will always used edge-triggered state elements (FFs), not level sensitive elements (latches). ynchronous vs Asynchronous Inputs ynchronous input: Output will change after active clock edge Asychronous input: Output changes independent of clock tate elements often have async set, reset control. input is synchronous with respect to lk, are asynchronous. output affected by, independent of. Async inputs are dominant over lk. B /99 7 B /99 FF with async control FF iming input (FF) Propagation elay 2: will change some propagation delay after change in. Value of is based on input for FF. 2, 2: will change some propagation delay after change on input, input ote that there is O propagation delay 2 for FF! is a ynchronous IPU, no prop delay value for synchronous inputs B /99 9 B /99 etup, old imes ynchronous inputs (e.g. ) have etup, old time specification with respect to the OK input etup ime: the amount of time the synchronous input () must be stable before the active edge of clock old ime: the amount of time the synchronous input () must be stable after the active edge of clock. B /99 changing etup, old ime t su t hd table changing If changes on input violate either setup or hold time, then correct FF operation is not guaranteed. etup/old measured around active clock edge. B /99 2

3 egisters he most common sequential building block is the register. A register is bits wide, and has a load line for loading in a new value into the register. egister contents do not change I unless = on active edge of clock. K A OU A FF is O a register! FF contents change every clock edge. A used to asynchronously clear the register B /99 3 I K A Bit egister using FF, Mux 2/ Mux FF ote that FF simply loads old value when =. FF is loaded every clock cycle. OU B /99 4 I K A lk d* dclk Bit egister using ated lock d* FF dclk OU FF aves power over previous design since FF is not clocked every clock cycle. Many FPAs offer an enabled FF as an integrated unit. ating can be optimized at transistor level in enabled FF. B /99 5 ounter Very useful sequential building block. Used to generate memory addresses, or keep track of the number of times a datapath operation is performed. I K _ A asserted loads counter with I value. _ asserted will increment counter on next active clock edge. A will asynchronously clear the counter. B /99 6 _ I K One way to build a ounter Incrementer I FF I Incrementer: ombinational Building Block tc... I I2 When =, = I + When =, = I I I A 2 B /99 7 B /99

4 ounter Operation ounter iming ( Bit register) ounter A K Aclr lk n + in + Op Async lr oad Increment old in $ 5 $ A ntr oad $ F $ 3 Inc old out $ $ A $ A $ A2 B /99 9 B /99 2 I K Another ounter (ntr B ) Incrementer FF I Aclr lk ounter Operation ounter B n + in + Op Async lr oad Increment old in+ oad Inc A =, = will load an incremented version of in B /99 2 B /99 22 ynchronous vs Asynchronous lear he A line is tied to the asynchronous reset of the FF Asynchronous clear is independent of clock, will occur anytime clear is asserted Usually tied to Power-On-eset (PO) circuit ot very useful for normal operation since any glitch on A will clear the counter Would like a ynchronous lear input () in which the clear operation takes place on the next active clock edge. I K A ntr A with Input Incrementer I FF B /99 23 B /99 24

5 Aclr clr ounter Operation ounter A with lk n + in + Op Async lr ync lr oad Increment old K Parallel ata ransfer o transfer data between two computers, we can do it in parallel: lk P [7:] P U U # #2 $ 5 $ A $ F $ 3 $ 75 $ 3 B /99 25 Parallel ata transfer requires a lot of lines to be run between computers; cabling be expensive, and bulky. ot practical for long distances. B /99 26 K erial ata ransfer We can transfer data in serial fashion, e.g., one bit at a time. lk P P U U # #2 bit bit bit2 bit3 bit4 bit5 bit6 bit7 $ 5 =, data transmitted B to MB B /99 27 More on erial ata ransfer? erial data transfer is more common than data parallel communication because less wires than parallel data transfer, can be run longer distances ata can be transferred either B (least significant bit) to MB (most significant bit) or vice-versa Most common is B to MB o implement serial data transfer we need a sequential building block that is called a IF register. B /99 2 hift egister Very useful sequential building block. Used to perform either parallel to serial data conversion or serial to parallel data conversion. I K A I I F OU asserted loads register with I value. asserted will shift data on next active clock edge. A is async clear. I is serial data in. ook at B of OU for serial data out. B /99 29 K in $ 5 OU $ $ 5 OU (B) hift egister iming (I = ) $ 42 $ 2 $ $ $ 4 $ 2 B /99 3

6 Understanding the shift operation MB B $5 = I = $42 = st right shift I = $2 = 2nd right shift I = $ = 3rd right shift tc. B /99 3 ight hift vs eft hift A right shift is MB to B In: I Out: I A left shift is B to MB In: I Out: I B /99 32 ombinational ight hifter We need a combinational block that can either shift right or pass data unchanged I I When =, = shifted right by position. When =, = I I I I I I I I I bit ombinational I hifter Implementation When =, then: = 3 2 When =, then: = I 3 2 (right shifted by one position) B /99 33 B /99 34 I I I I I 4-bit ombinational F hifter Implementation When =, then: = 3 2 hift egister (ight shift) Implementation I ight hifter I I I I I 2 3 When =, then: = 2 I (left shifted by one position) I K A FF B /99 35 B /99 36

7 A[7..] K A A I_A PU A I F erial ommunication A[7..] A B[7..] K B A I_B PU B I F B[7..] K A hift egister iming (I_A = ) A A $ $ 5 $ 42 $ 2 $ $ $ 4 $ 2 $ A $ B $ $ $ 4 $ A $ 5 $ 2 $ 4 $A $ 5 $ B /99 37 B /99 3 omments on hift operation ook clock cycles to serially send the bits in PU A to PU B. hift egister at PU A ended up at $; hift egister at PU B ended up with PU A value ($5) Initial contents of PU B shift register does not matter ata shifted out B to MB from PUA to PUB. ote that data enters the MB at PUB and progresses toward the B. equential ystem escription he outputs of the flip-flops form a state vector A particular set of outputs is the Present tate (P) he state vector that occurs at the next discrete time (clock edge for synchronous designs) is the ext tate () A sequential circuit described in terms of state is a Finite tate Machine (FM) ot all sequential circuits are described this way; i.e., registers are not described as FMs yet a register is a sequential circuit. B /99 39 B /99 4 escribing FMs tate ables tate quations tate iagrams Algorithmic tate Machine (AM) harts Preferred method in this class descriptions B /99 4 xample tate Machine 2 tate iagram (Bubble iagram) 2 AM hart B /99 42

8 tate Assignment tate assignment is the binary coding used to represent the states iven states, need at least log 2 () FFs to encode the states (i.e. 3 states, need at least 2 FFs for state information). =, =, 2 = (FM is now a modulo 3 counter) o not always have to use the fewest possible number of FFs. A common encoding is One-ot encoding - use one FF per state. =, =, 2 = tate assignment affects speed, gate count of FM B /99 43 FM Implementation Use FFs, tate assignment: =, =, 2 = P Inc + tate able quations x x x x = Inc + Inc = Inc + Inc x x x x B /99 44 Minimize quations (if desired) Inc x x Inc x x = Inc + Inc = Inc + Inc I ustom counters atapath control FM Usage + FM ontrol (reg load lines, mux selects) OU B /99 45 B /99 46 ummary We will be describing sequential systems via V and AM charts Use AM chart for human reader, V to allow synthesis of the design ynthesis will perform combinational minimization, but not state reduction. Will use common sequential building blocks extensively egisters, ounters, hift registers, Memories Basic storage element will be FF ynchronous (edge-triggered) design methodology B /99 47

Page 1. Last time we looked at: latches. flip-flop

Page 1. Last time we looked at: latches. flip-flop Last time we looked at: latches flip flops We saw that these devices hold a value depending on their inputs. A data input value is loaded into the register on the rise of the edge. Some circuits have additional