Lecture 02: Digital Logic Review

Transcription

1 CENG 3420 Lecture 02: Digital Logic Review Bei Yu CENG3420 L02 Digital Logic. 1 Spring 2017

2 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017

3 Review: The Instruction Set Architecture (ISA) software instruction set architecture hardware The interface description separating the software and hardware CENG3420 L02 Digital Logic. 3 Spring 2017

4 Analog vs. Digital Analog Signal q Vary in a smooth way over time q Analog data are continuous valued Example: audio, video Digital Signal q Maintains a constant level then changes to another constant level (generally operate in one of the two states) q Digital data are discrete valued Example: computer data CENG3420 L02 Digital Logic. 4 Spring 2017

5 Number Systems q An ordered set of symbols, called digits, with relations defined for addition, subtraction, multiplication, and division q Radix or base of the number system is the total number of digits allowed in the number system q Commonly used numeral systems CENG3420 L02 Digital Logic. 5 Spring 2017

6 q In the 2009 film Avatar, Na'vi race employs an octal numeral system. CENG3420 L02 Digital Logic. 6 Spring 2017

7 Conversion from Decimal Integer q Step 1: Divide the decimal number by the radix (number base) q Step 2: Save the remainder (first remainder is the least significant digit) q Repeat steps 1 and 2 until the quotient is zero q Result is in reverse order of remainders CENG3420 L02 Digital Logic. 7 Spring 2017

8 EX: L02-1 q EX1: Convert 36 8 to binary value q EX2: Convert to binary value CENG3420 L02 Digital Logic. 8 Spring 2017

9 Unsigned Binary Representation Hex Binary Decimal 0x x x x x x x x x x xFFFFFFFC xFFFFFFFD xFFFFFFFE xFFFFFFFF bit weight bit position bit CENG3420 L02 Digital Logic. 9 Spring 2017

10 Signed Binary Representation 2 sc binary decimal -2 3 = (2 3-1) = complement all the bits and add a 1 and add a complement all the bits CENG3420 L02 Digital Logic. 10 Spring =

11 EX: L02-2 q For an n-bit signed binary numeral system, what s the largest positive number and the smallest negative number? CENG3420 L02 Digital Logic. 11 Spring 2017

12 Digital Circuits Digital circuits generally contain two parts: Combinational logic Sequential logic Combinational circuits consist of logic gates with inputs and outputs The outputs at any instance of time depend only on the combination of the input values based on logic operations such as AND, OR etc. Sequential circuits, in addition to inputs and outputs also have storage elements, therefore the output depends on both the current inputs as well as the stored values CENG3420 L02 Digital Logic. 12 Spring 2017

13 Digital Signal Representation q Active HIGH High voltage means On q Active LOW Low voltage means On 5.0 V Logic 0 Logic 1 False Off LOW No Open switch True On HIGH Yes Closed switch HIGH (1) LOW (0) 4.0 V 3.0 V 2.0 V 1.0 V 0.0 V CENG3420 L02 Digital Logic. 13 Spring 2017

14 Logic Gates NOT (Invertor) AND OR Invertor schematic view NAND NOR XOR XNOR q What is the schematic view of an AND gate? CENG3420 L02 Digital Logic. 14 Spring 2017

15 EX: L02-3 q Please draw NOR gate schematic view CENG3420 L02 Digital Logic. 15 Spring 2017

16 Truth Table q A means for describing how a logic circuit s output depends on the logic levels present at the circuit s inputs q The number of input combinations will equal 2 N for an N-input truth table A B Logic Circuit Y Inputs Output A B Y CENG3420 L02 Digital Logic. 16 Spring 2017

17 EX: L02-4 Determine the true table of a three-input AND gate CENG3420 L02 Digital Logic. 17 Spring 2017

18 Combinational Circuits Input X.. Combinational Circuits.. Output Z Z = F(X) In combinational circuits, the output at any time is a direct function of the applied external inputs CENG3420 L02 Digital Logic. 18 Spring 2017

19 Design Procedure of Combinational Circuits Circuit Specification Truth Table How many input/output? Minimization K-maps, Algebraic Manipulation, CAD tools Logic Diagram CENG3420 L02 Digital Logic. 19 Spring 2017

20 EX: L02-5 q Implement AB+CD using NAND gates only CENG3420 L02 Digital Logic. 20 Spring 2017

21 Propagation Delay q The delay when the signal arrives at the input of a circuit, and when the output of the circuit changes, is called the propagation delay q A circuit is considered to be fast, if its propagation delay is small (ideally as close to 0 as possible) X Y Z Delay between input (X, Y) and change in output Z CENG3420 L02 Digital Logic. 21 Spring 2017

22 Timing Diagram q The inputs to a circuit can be changed over time. q The timing diagram shows the values of the input signals to a circuit with the passage of time, in the form of a waveform q It also shows a waveform for the output Inputs X Y Propagation Delay of the Circuit = τ Output Z Timing Diagram for an AND gate Time CENG3420 L02 Digital Logic. 22 Spring 2017

23 Power Consumption V DD Dynamic Power V o C L V DD2 /2 V i C L Ground CENG3420 L02 Digital Logic. 23 Spring 2017

24 Fanin q Fanin of a gate is the number of inputs to the gate q For a 3-input OR gate, the fanin = 3 q There is a limitation on the fanin for any gate q In CMOS IC technology, higher fanin implies slower gates (higher propagation delays) CENG3420 L02 Digital Logic. 24 Spring 2017

25 Fanout q Fanout is the number of gates that can be driven by a driver gate q The driven gate is called the load gate q There is a limit to the number of load gates that can be driven by a driver gate Fanout = 3 CENG3420 L02 Digital Logic. 25 Spring 2017

26 Buffers q Buffers have a single input and a single output, where output = input q Buffers help increase the driving capability of a circuit by increasing the fanout q Drive strength: how much load a gate can drive q Greater drive strength, fanout gates (dis)charged quickly CENG3420 L02 Digital Logic. 26 Spring 2017

27 How to increase drive strength? q Reduce resistance -> Increase output current Increase transistor size with gate Parallel a number of transistors NAND BUF_X1 BUF_X4 BUF_X16 CENG3420 L02 Digital Logic. 27 Spring 2017

28 Decoder n inputs. n-to-2 n Decoder... 2 n outputs q Information is represented by binary codes q Decoding - the conversion of an n-bit input code to an m-bit output code with n <= m <= 2 n such that each valid code word produces a unique output code q Circuits that perform decoding are called decoders q A decoder is a minterm generator CENG3420 L02 Digital Logic. 28 Spring 2017

29 Decoder (Use Cases) q Decode a 3-bit op-codes: q Home automation: op0 op1 op2 3-to-8 Decoder Add Sub And Xor Not Load Store Jump C 0 C 1 2-to-4 Decoder Light A/C Door Light-A/C Load a Add b Store c.. CENG3420 L02 Digital Logic. 29 Spring 2017

30 Decoder-Based Circuits X Y Z C S S = (1,2,4,7) C = (3,5,6,7) 3 inputs and 8 possible minterms 3-to-8 decoder can be used for implementing this circuit Src: Mano s book CENG3420 L02 Digital Logic. 30 Spring 2017

31 Encoder 2 n inputs... 2 n -to-n Encoder. n outputs q Encoding - the opposite of decoding - the conversion of an m-bit input code to a n-bit output code such that each valid code word produces a unique output code q Circuits that perform encoding are called encoders q An encoder has 2 n (or fewer) input lines and n output lines which generate the binary code corresponding to the input values q Typically, an encoder converts a code containing exactly one bit that is 1 to a binary code corresponding to the position in which the 1 appears. CENG3420 L02 Digital Logic. 31 Spring 2017

32 Multiplexers q Directs one of 2 n input to the output q Input to output direction is done based on a set of n select bits 2 n inputs 2 n x 1 MUX one output n select lines CENG3420 L02 Digital Logic. 32 Spring 2017

33 MUX-based Design (n-1 Select lines) A B C F F = C C D 0 F(A,B,C)= (1,2,6,7) F = C F = 0 C 0 1 D 1 D 2 D 3 S S 1 0 A B F F = 1 CENG3420 L02 Digital Logic. 33 Spring 2017

34 Combinational vs Sequential inputs X Combinational Circuits outputs Z q A combinational circuit: q At any time, outputs depends only on inputs Changing inputs changes outputs q History is ignored! CENG3420 L02 Digital Logic. 34 Spring 2017

35 Combinational vs Sequential inputs X present state Combinational Circuits Memory outputs Z next state q A sequential circuit: q outputs depends on inputs and previous inputs Previous inputs are stored as binary information into memory The stored information at any time defines a state q next state depends on inputs and present state CENG3420 L02 Digital Logic. 35 Spring 2017

36 Examples of sequential systems Traffic light ATM Vending machine CENG3420 L02 Digital Logic. 36 Spring 2017

37 Types of Sequential Circuits q Two types of sequential circuits: Synchronous: The behavior of the circuit depends on the input signal values at discrete intervals of time (also called clocked) Asynchronous: The behavior of the circuit depends on the order of change of the input signals at any instance of time (continuous) CENG3420 L02 Digital Logic. 37 Spring 2017

38 Design A Latch q Store one bit of information: cross-coupled invertor = q How to change the value stored? R: reset signal S: set signal SR-Latch CENG3420 L02 Digital Logic. 38 Spring 2017

39 EX: L02-6 q What s the Q value based on different R, S inputs? q S=R=1: q S=0,R=1: q S=1,R=0: q S=R=0: CENG3420 L02 Digital Logic. 39 Spring 2017

40 Design A Flip-Flop q Based on Gated Latch = q Master-slave positive-edge-triggered D flip-flop CENG3420 L02 Digital Logic. 40 Spring 2017

41 Latch and Flip-Flop q Latch is level-sensitive q Flip-flop is edge triggered CENG3420 L02 Digital Logic. 41 Spring 2017

42 Timing Diagrams (optional) Contamination and Propagation Delays t pd Logic Prop. Delay A Combinational Logic Y A Y t cd t pd t cd Logic Cont. Delay t pcq Latch/Flop Clk-Q Prop Delay clk clk t setup t hold t ccq Latch/Flop Clk-Q Cont. Delay D Flop Q D t pcq t pdq Latch D-Q Prop Delay Q t ccq t pcq t setup t hold Latch D-Q Cont. Delay Latch/Flop Setup Time Latch/Flop Hold Time D clk Latch Q clk D Q t setup t hold t t ccq pcq t cdq t pdq CENG3420 L02 Digital Logic. 42 Spring 2017

43 Registers 0 1 n-1 q A register is a group of flip-flops. q An n-bit register is made of n flip-flips and can store n bits q A register may have additional combinational gates to perform certain operations CENG3420 L02 Digital Logic. 43 Spring 2017

44 4-Bit Register q A simple 4-bit register can be made with 4 D-FF q Common Clock At each positive-edge, 4 bits are loaded in parallel Previous data is overwritten q Common Clear Asynchronous clear When Clear = 0, all FFs are cleared; i.e. 0 is stored. CENG3420 L02 Digital Logic. 44 Spring 2017

45 4-bit Shift Register Serial-in and Serial-out (SISO) q A simple 4-bit shift register can be made with 4 D-FF q Common Clock At each positive-edge, 1 bit is shifted in Rightmost bit is discarded q Which direction this register is shifting? CENG3420 L02 Digital Logic. 45 Spring 2017

46 Universal Shift Register (cont.) CENG3420 L02 Digital Logic. 46 Spring 2017