ENGIN 112 Intro to Electrical and Computer Engineering
|
|
- Mabel Poole
- 6 years ago
- Views:
Transcription
1 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 28 Timing Analysis
2 Overview Circuits do not respond instantaneously to input changes Predictable delay in transferring inputs to outputs Propagation delay Sequential circuits require a periodic clock Goal: analyze clock circuit to determine maximum clock frequency Requires analysis of paths from flip-flop outputs to flip-flop inputs Even after inputs change, output signal of circuit maintains original output for short time Contamination delay
3 Sequential Circuits Sequential circuits can contain both combinational logic and edge-triggered flip flops A clock signal determines when data is stored in flip flops Goal: How fast can the circuit operate? Minimum clock period: T min Maximum clock frequency: f max Maximum clock frequency is the inverse of the minimum clock period 1/T min = f max Clock Period Clock
4 Combinational Logic Timing: Inverter A Y A Y t cd t pd Combinational logic is made from electronic circuits An input change takes time to propagate to the output The output remains unchanged for a time period equal to the contamination delay, t cd The new output value is guaranteed to valid after a time period equal to the propagation delay, t pd
5 Combinational Logic Timing: XNOR Gate A B C A B C t cd t pd The output is guaranteed to be stable with old value until the contamination delay Unknown values shown in waveforms as Xs The output is guaranteed to be stable with the new value after the propagation delay
6 Combinational Logic Timing: complex circuits = 2ns T cd = 1ns A Circuit X = 3ns T cd = 1ns C A B Circuit X C B = 5ns T cd = 1ns Propagation delays are additive Locate the longest combination of t pd Contamination delays may not be additive Locate the shortest path of t cd Find propagation and contamination delay of new, combined circuit
7 Clocked Device: Contamination and Propagation Delay D Q D Clk Q t cd t Clk-Q Timing parameters for clocked devices are specified in relation to the clock input (rising edge) Output unchanged for a time period equal to the contamination delay, t cd after the rising clock edge New output guaranteed valid after time equal to the propagation delay, t Clk-Q Follows rising clock edge
8 Clocked Devices: Setup and Hold Times D Q D t s t h Clk Q Timing parameters for clocked devices are specified in relation to the clock input (rising edge) D input must be valid at least t s (setup time) before the rising clock edge D input must be held steady t h (hold time) after rising clock edge Setup and hold are input restrictions Failure to meet restrictions causes circuit to operate incorrectly
9 Edge-Triggered Flip Flop Timing D CLK t h = hold time t s = setup time The logic driving the flip flop must ensure that setup and hold are met Timing values (t cd t pd t Clk-Q t s t h )
10 Analyzing Sequential Circuits CLK D T Clk-Q = 5ns Logic T Clk-Q = 5 ns T s = 2 ns D Q D Q FFA X = 5ns G Y FFB Z What is the minimum time between rising clock edges? T min = T CLK-Q (FFA) + (G) + T s (FFB) Trace propagation delays from FFA to FFB Draw the waveforms! F max =
11 Analyzing Sequential Circuits = 4ns Logic F CLK Logic H D Q D Q FFA T Clk-Q = 5ns X = 5ns T Clk-Q = 4 ns T s = 2 ns What is the minimum clock period (T min ) of this circuit? Hint: evaluate all FF to FF paths Y FFB Z Maximum clock frequency is 1/T min
12 Analyzing Sequential Circuits = 4ns F max = Logic F CLK Logic H D Q D Q FFA T Clk-Q = 5ns X = 5ns T Clk-Q = 4 ns T s = 2 ns Path FFA to FFB T Clk-Q (FFA) + (H) + T s (FFB) = 5ns + 5ns + 2ns = 12ns Path FFB to FFB T CLK-Q (FFB) + (F) + (H) + T s (FFB) = 4ns + 4ns + 5ns + 2ns Y FFB Z
13 Analyzing Sequential Circuits: Hold Time Violation T cd = 1ns T cd = 2ns T h = 2 ns CLK D X Logic D Q D Q FFA G Y FFB Z One more issue: make sure Y remains stable for hold time (T h ) after rising clock edge Remember: contamination delay ensures signal doesn t change How long before first change arrives at Y? T cd (FFA) + T cd (G) >= T h 1ns + 2ns > 2ns
14 Analyzing Sequential Circuits: Hold Time Violations T cd = 1ns All paths must satisfy requirements Logic F CLK Logic H D Q D Q FFA T ClD = 1ns T ClD = 1 ns T h = 2 ns Path FFA to FFB T CD (FFA) + T CD (H) > T h (FFB) = 1 ns + 2ns > 2ns X T cd = 2ns Y FFB Z Path FFB to FFB T CD (FFB) + T CD (F) + T Cd (H) > T h (FFB) = 1ns + 1ns + 2ns > 2ns
15 Summary Maximum clock frequency is a fundamental parameter in sequential computer systems Possible to determined clock frequency from propagation delays and setup time The longest path determines the clock frequenct All flip-flop to flip-flop paths must be checked Hold time are satisfied by examining contamination delays The shortest contamination delay path determines if hold times are met Check handout for more details and examples.
EE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization Spring 2018 Timing Analysis Lecture 11: 1 Announcements Lab report guidelines are uploaded on CMS As part of the assignment for Lab 3 report Lab 4(A) prelab
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018
UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationTiming Issues in FPGA Synchronous Circuit Design
ECE 428 Programmable ASIC Design Timing Issues in FPGA Synchronous Circuit Design Haibo Wang ECE Department Southern Illinois University Carbondale, IL 62901 1-1 FPGA Design Flow Schematic capture HDL
More informationLecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers Friday s class will be a lecture rather
More informationEC4205 Microprocessor and Microcontroller
EC4205 Microprocessor and Microcontroller Webcast link: https://sites.google.com/a/bitmesra.ac.in/aminulislam/home All announcement made through webpage: check back often Students are welcome outside the
More information! Review: Sequential MOS Logic. " SR Latch. " D-Latch. ! Timing Hazards. ! Dynamic Logic. " Domino Logic. ! Charge Sharing Setup.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 29, 206 Timing Hazards and Dynamic Logic Lecture Outline! Review: Sequential MOS Logic " SR " D-! Timing Hazards! Dynamic Logic "
More informationECE 551: Digital System Design & Synthesis
ECE 551: Digital System Design & Synthesis Lecture Set 9 9.1: Constraints and Timing 9.2: Optimization (In separate file) 03/30/03 1 ECE 551 - Digital System Design & Synthesis Lecture 9.1 - Constraints
More informationProject Board Game Counter: Digital
Project 1.3.3 Board Game Counter: Digital Introduction Just a few short weeks ago, most of you knew little or nothing about digital electronics. Now you are about to build and simulate a complete design.
More informationWe ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits
Basic Timing Issues We ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits The fundamental timing issues we considered then apply
More informationModule -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) Saving a few bucks at toll booths 5) Edge-triggered Registers 1 General Table Lookup Synthesis A B 00
More informationIn this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems.
1 In this lecture, we will first examine practical digital signals. Then we will discuss the timing constraints in digital systems. The important concepts are related to setup and hold times of registers
More information! Sequential Logic. ! Timing Hazards. ! Dynamic Logic. ! Add state elements (registers, latches) ! Compute. " From state elements
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: April 2, 2019 Sequential Logic, Timing Hazards and Dynamic Logic Lecture Outline! Sequential Logic! Timing Hazards! Dynamic Logic 4 Sequential
More informationEECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics
EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics I. OVERVIEW I.A Combinational vs. Sequential Logic Combinational Logic (everything so far): Outputs depend entirely on
More informationComputer Architecture (TT 2012)
Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture
More informationTiming analysis can be done right after synthesis. But it can only be accurately done when layout is available
Timing Analysis Lecture 9 ECE 156A-B 1 General Timing analysis can be done right after synthesis But it can only be accurately done when layout is available Timing analysis at an early stage is not accurate
More informationlogic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs
Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC0 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC0 74HC/HCT/HCU/HCMOS Logic Package Information The IC0 74HC/HCT/HCU/HCMOS
More informationCMOS Digital Integrated Circuits Analysis and Design
CMOS Digital Integrated Circuits Analysis and Design Chapter 8 Sequential MOS Logic Circuits 1 Introduction Combinational logic circuit Lack the capability of storing any previous events Non-regenerative
More informationCD54HC273, CD74HC273, CD54HCT273, CD74HCT273
Data sheet acquired from Harris Semiconductor SCHS174B February 1998 - Revised May 2003 CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset [ /Title (CD74
More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS
More informationStatic Timing Overview with intro to FPGAs. Prof. MacDonald
Static Timing Overview with intro to FPGAs Prof. MacDonald Static Timing In the 70 s timing was performed with Spice simulation In the 80 s timing was included in Verilog simulation to determine if design
More informationINF3430 Clock and Synchronization
INF3430 Clock and Synchronization P.P.Chu Using VHDL Chapter 16.1-6 INF 3430 - H12 : Chapter 16.1-6 1 Outline 1. Why synchronous? 2. Clock distribution network and skew 3. Multiple-clock system 4. Meta-stability
More informationCS/EE Homework 9 Solutions
S/EE 260 - Homework 9 Solutions ue 4/6/2000 1. onsider the synchronous ripple carry counter on page 5-8 of the notes. Assume that the flip flops have a setup time requirement of 2 ns and that the gates
More informationChapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1
Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates
More informationDM74ALS169B Synchronous Four-Bit Up/Down Counters
Synchronous Four-Bit Up/Down Counters General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74ALS169B
More informationCS152 Computer Architecture and Engineering Lecture 3: ReviewTechnology & Delay Modeling. September 3, 1997
CS152 Computer Architecture and Engineering Lecture 3: ReviewTechnology & Delay Modeling September 3, 1997 Dave Patterson (httpcsberkeleyedu/~patterson) lecture slides: http://www-insteecsberkeleyedu/~cs152/
More informationDM74AS169A Synchronous 4-Bit Binary Up/Down Counter
Synchronous 4-Bit Binary Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74AS169
More informationB.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics
B.E. SEMESTER III (ELECTRICAL) SUBJECT CODE: X30902 Subject Name: Analog & Digital Electronics Sr. No. Date TITLE To From Marks Sign 1 To verify the application of op-amp as an Inverting Amplifier 2 To
More informationAnnouncements. Advanced Digital Integrated Circuits. Midterm feedback mailed back Homework #3 posted over the break due April 8
EE241 - Spring 21 Advanced Digital Integrated Circuits Lecture 18: Dynamic Voltage Scaling Announcements Midterm feedback mailed back Homework #3 posted over the break due April 8 Reading: Chapter 5, 6,
More informationChapter 2 Combinational Circuits
Chapter 2 Combinational Circuits SKEE2263 Digital Systems Mun im/ismahani/izam {munim@utm.my,e-izam@utm.my,ismahani@fke.utm.my} February 23, 26 Why CMOS? Most logic design today is done on CMOS circuits
More informationENGG1015: lab 3. Sequential Logic
ENGG1015: lab 3 Sequential Logic 1 st Semester 2012-13 This lab explores the world of sequential logic design. By the end of this lab, you will have implemented a working prototype of a Ball ounter that
More informationBrought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja.
Brought to you by Priti Srinivas Sajja PS01CMCA02 Course Content Tutorial Practice Material Acknowldgement References Website pritisajja.info Multiplexer Means many into one, also called data selector
More informationMux-Based Latches. Lecture 8. Sequential Circuits 1. Mux-Based Latch. Mux-Based Latch. Negative latch (transparent when CLK= 0)
Mux-Based Latches Lecture 8 equential Circuits Negative latch (transparent when = 0) Positive latch (transparent when = ) Peter Cheung epartment of Electrical & Electronic Engineering Imperial College
More informationCD74HC73, CD74HCT73. Dual J-K Flip-Flop with Reset Negative-Edge Trigger. Features. Description. Ordering Information. Pinout
Data sheet acquired from Harris Semiconductor SCHS134 February 1998 CD74HC73, CD74HCT73 Dual J-K Flip-Flop with Reset Negative-Edge Trigger [ /Title (CD74 HC73, CD74 HCT73 ) /Subject Dual -K liplop Features
More informationCourse Outline Cover Page
College of Micronesia FSM P.O. Box 159 Kolonia, Pohnpei Course Outline Cover Page Digital Electronics I VEE 135 Course Title Department and Number Course Description: This course provides the students
More informationLOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1
LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design
More informationThe Non Inverting Buffer
The Non Inverting Buffer We now spend some time investigating useful circuit elements that do not directly implement Boolean functions. The first element is the non inverting buffer. This is logically
More informationChapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/30/2008
Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/3/28 6/3/28 Computer Engineering Basic Element for Sequential CircuitsSR Latch Latch Store one-bit information (two states of and ) Two inputs,
More informationEECS 150 Homework 4 Solutions Fall 2008
Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring
More informationLecture 9: Clocking for High Performance Processors
Lecture 9: Clocking for High Performance Processors Computer Systems Lab Stanford University horowitz@stanford.edu Copyright 2001 Mark Horowitz EE371 Lecture 9-1 Horowitz Overview Reading Bailey Stojanovic
More informationDr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006
COE/EE2DI4 Midterm Test #1 Fall 2006 Page 1 Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 Instructions: This examination paper includes 10 pages and 20 multiple-choice questions starting
More informationChapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011
Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7//2 Ver. 72 7//2 Computer Engineering What is a Sequential Circuit? A circuit consists of a combinational logic circuit and internal memory
More informationData Logger by Carsten Kristiansen Napier University. November 2004
Data Logger by Carsten Kristiansen Napier University November 2004 Title page Author: Carsten Kristiansen. Napier No: 04007712. Assignment title: Data Logger. Education: Electronic and Computer Engineering.
More informationCPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4
CPE/EE 427, CPE 527 VLSI Design I: Homeworks 3 & 4 1 2 3 4 5 6 7 8 9 10 Sum 30 10 25 10 30 40 10 15 15 15 200 1. (30 points) Misc, Short questions (a) (2 points) Postponing the introduction of signals
More information74ABT273 Octal D-Type Flip-Flop
Octal D-Type Flip-Flop General Description The ABT273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load
More informationIES Digital Mock Test
. The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More informationCS 61C: Great Ideas in Computer Architecture Lecture 10: Finite State Machines, Func/onal Units. Machine Interpreta4on
CS 61C: Great Ideas in Computer Architecture Lecture 10: Finite State Machines, Func/onal Units Instructor: Sagar Karandikar sagark@eecs.berkeley.edu hep://inst.eecs.berkeley.edu/~cs61c 1 Levels of RepresentaJon/
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS August 29, 2002 John Wawrzynek Fall 2002 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationEECS 141: FALL 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you
More informationCourse Overview. Course Overview
Course Overview Where does this course fit into the Electrical Engineering curriculum? Page 5 Course Overview Where does this course fit into the Computer Engineering curriculum? Page 6 3 Course Content
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 4.2.1: Learn More Liang Liu liang.liu@eit.lth.se 1 Outline Crossing clock domain Reset, synchronous or asynchronous? 2 Why two DFFs? 3 Crossing clock
More informationLogic 0 Logic To provide an output load (or two) 5 Voltage Measurement Point V CC +5 74LS00 GND
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 1 Logic Analyzers, Digital Oscilloscopes, and
More informationCD74HC534, CD74HCT534, CD74HC564, CD74HCT564
Data sheet acquired from Harris Semiconductor SCHS188 January 1998 CD74HC534, CD74HCT534, CD74HC564, CD74HCT564 High Speed CMOS Logic Octal D-Type Flip-Flop, Three-State Inverting Positive-Edge Triggered
More informationDigital Electronics Electronics Technology
Digital Electronics Electronics Technology Landon ohnson hift egisters DIGITAL INTEGATED CICUIT MALL CALE INTEGATION LE THAN 12 GATE MEDIUM CALE INTEGATION 12 TO 99 GATE LAGE CALE INTEGATION 100 TO 9999
More informationEC O4 403 DIGITAL ELECTRONICS
EC O4 403 DIGITAL ELECTRONICS Asynchronous Sequential Circuits - II 6/3/2010 P. Suresh Nair AMIE, ME(AE), (PhD) AP & Head, ECE Department DEPT. OF ELECTONICS AND COMMUNICATION MEA ENGINEERING COLLEGE Page2
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More informationLIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM
LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation
More informationCD54/74HC74, CD54/74HCT74
CD54/74HC74, CD54/74HCT74 Data sheet acquired from Harris Semiconductor SCHS124A January 1998 - Revised May 2000 Dual D Flip-Flop with Set and Reset Positive-Edge Trigger Features Description [ /Title
More information54AC191 Up/Down Counter with Preset and Ripple Clock
54AC191 Up/Down Counter with Preset and Ripple Clock General Description The AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature
More informationCSE 260 Digital Computers: Organization and Logical Design. Midterm Solutions
CSE 260 Digital Computers: Organization and Logical Design Midterm Solutions Jon Turner 2/28/2008 1. (10 points). The figure below shows a simulation of the washu-1 processor, with some items blanked out.
More informationPHYSICS 536 Experiment 14: Basic Logic Circuits
PHYSICS 5 Experiment 4: Basic Logic Circuits Several T 2 L ICs will be used to illustrate basic logic functions. Their pin connections are shown in the following sketch, which is a top view. 4 2 9 8 +5V
More informationElectronics. Digital Electronics
Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital
More informationHIGH LOW Astable multivibrators HIGH LOW 1:1
1. Multivibrators A multivibrator circuit oscillates between a HIGH state and a LOW state producing a continuous output. Astable multivibrators generally have an even 50% duty cycle, that is that 50% of
More informationDIGITAL ELECTRONICS: LOGIC AND CLOCKS
DIGITL ELECTRONICS: LOGIC ND CLOCKS L 9 INTRO: INTRODUCTION TO DISCRETE DIGITL LOGIC, MEMORY, ND CLOCKS GOLS In this experiment, we will learn about the most basic elements of digital electronics, from
More informationBaker Ch 13: Clocked Circuits
Topics: 1. Intro Foil 2. CMOS Transmission Gate Definition 3. Delay of TG 4. Applications of TG-Selector 5. Applications of TG-MUX 6. TG vs. Pass Transistor 7. Applications of TG-OR, XOR, XNOR 8. SR Latch-NAND,
More informationEE 330 Lecture 44. Digital Circuits. Dynamic Logic Circuits. Course Evaluation Reminder - All Electronic
EE 330 Lecture 44 Digital Circuits Dynamic Logic Circuits Course Evaluation Reminder - All Electronic Digital Building Blocks Shift Registers Sequential Logic Shift Registers (stack) Array Logic Memory
More informationCS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON
CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Instructor: Andy Phelps TAs: Newsha Ardalani, Peter Ohmann, and Jai Menon Midterm Examination 2 In Class (50 minutes) Wednesday,
More informationHIGH-performance microprocessors employ advanced circuit
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 5, MAY 1999 645 Timing Verification of Sequential Dynamic Circuits David Van Campenhout, Student Member, IEEE,
More informationE2.11/ISE2.22 Digital Electronics II
E2./IE2.22 igital Electronics II roblem heet (uestion ratings: =Easy,, E=Hard. ll students should do questions rated, or as a minimum). The diagram shows three gates in which one input (OTOL) is being
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationSRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI
SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF
More informationDM74ALS174 DM74ALS175 Hex/Quad D-Type Flip-Flops with Clear
Hex/Quad D-Type Flip-Flops with Clear General Description These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. Both have an asynchronous clear input, and
More informationEXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation)
EXPERIMENT 2: Introduction to Cadence Tools (Schematic Capture and Circuit Simulation) PURPOSE The purpose of this experiment is to introduce you to schematic capture and logic simulation. Primarily, you
More informationBy: Dr. Ahmed ElShafee
Lecture (03) COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II Design of Circuits with Limited Gate Fan In In
More informationCHAPTER 5 DESIGNS AND ANALYSIS OF SINGLE ELECTRON TECHNOLOGY BASED MEMORY UNITS
208 CHAPTER 5 DESIGNS AND ANALYSIS OF SINGLE ELECTRON TECHNOLOGY BASED MEMORY UNITS 5.1 INTRODUCTION The objective of this chapter is to design and verify the single electron technology based memory circuits
More information74ABT377 Octal D-Type Flip-Flop with Clock Enable
Octal D-Type Flip-Flop with Clock Enable General Description The ABT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all
More informationData Sheet. HCTL-2000 Quadrature Decoder/Counter Interface ICs HCTL-2000, HCTL-2016, HCTL-2020
HCTL-2000 Quadrature Decoder/Counter Interface ICs Data Sheet HCTL-2000, HCTL-2016, HCTL-2020 Description The HCTL-2000, 2016, 2020 are CMOS ICs that perform the quadrature decoder, counter, and bus interface
More information! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable!
More information74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The ALVC16500 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops
More informationEE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30
EE 330 Lecture 44 igital Circuits Ring Oscillators Sequential Logic Array Logic Memory Arrays Final: Tuesday May 2 7:30-9:30 Review from Last Time ynamic Logic Basic ynamic Logic Gate V F A n PN Any of
More informationLecture # 16 Logic with a State Dependent Device. Logic Gates How are they built in practice?
EECS 42 Introduction to Digital Electronics Andrew R. Neureuther These viewgraphs will be handed out in class 1/21/ Lecture # 16 Logic with a State Dependent Device S&O pp. 9-9, 4-6 (read for graphs and
More informationApplication Note, V 1.0, Feb AP C16xx. Timing, Reading the AC Characteristics. Microcontrollers. Never stop thinking.
Application Note, V 1.0, Feb. 2004 AP16004 C16xx Timing, Reading the AC Characteristics. Microcontrollers Never stop thinking. C16xx Revision History: 2004-02 V 1.0 Previous Version: - Page Subjects (major
More informationUsing IBIS Models for Timing Analysis
Application Report SPRA839A - April 2003 Using IBIS Models for Timing Analysis ABSTRACT C6000 Hardware Applications Today s high-speed interfaces require strict timings and accurate system design. To achieve
More informationLecture 19: Design for Skew
Introduction to CMOS VLSI Design Lecture 19: Design for Skew David Harris Harvey Mudd College Spring 2004 Outline Clock Distribution Clock Skew Skew-Tolerant Circuits Traditional Domino Circuits Skew-Tolerant
More informationTiming Verification of Sequential Domino Circuits
Timing Verification of Sequential Domino Circuits David Van Campenhout, Trevor Mudge, and Karem A. Sakallah Advanced Computer Architecture Laboratory EECS Department, University of Michigan Ann Arbor,
More informationFirst Optional Homework Problem Set for Engineering 1630, Fall 2014
First Optional Homework Problem Set for Engineering 1630, Fall 014 1. Using a K-map, minimize the expression: OUT CD CD CD CD CD CD How many non-essential primes are there in the K-map? How many included
More informationDM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters
DM74LS161A DM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting desig. The
More information6.111 Lecture # 19. Controlling Position. Some General Features of Servos: Servomechanisms are of this form:
6.111 Lecture # 19 Controlling Position Servomechanisms are of this form: Some General Features of Servos: They are feedback circuits Natural frequencies are 'zeros' of 1+G(s)H(s) System is unstable if
More information74AC74B DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR
DUAL D-TYPE FLIP FLOP WITH PRESET AND CLEAR HIGH SPEED: f MAX = 300MHz (TYP.) at V CC = 5V LOW POWER DISSIPATION: I CC = 2µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) 50Ω
More informationObsolete Product(s) - Obsolete Product(s)
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP HIGH SPEED: f MAX = 180MHz (TYP.) at V CC =5V LOW POWER DISSIPATION: I CC =1µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS: V IH =2V(MIN),V IL =0.8V(MAX)
More information74ACTQ821 Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs
Quiet Series 10-Bit D-Type Flip-Flop with 3-STATE Outputs General Description The ACTQ821 is a 10-bit D-type flip-flop with non-inverting 3-STATE outputs arranged in a broadside pinout. The ACTQ821 utilizes
More informationbus waveforms transport delta and simulation
bus waveforms transport delta and simulation Time Modelling and Data Flow Descriptions Modeling time in VHDL Different models of time delay Specify timing requirement Data flow descriptions Signal resolution
More informationM74HCT574TTR OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT NON INVERTING HIGH SPEED: f MAX = 50MHz (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.)
More informationDigital Systems Power, Speed and Packages II CMPE 650
Speed VLSI focuses on propagation delay, in contrast to digital systems design which focuses on switching time: A B A B rise time propagation delay Faster switching times introduce problems independent
More information