EECS 150 Homework 4 Solutions Fall 2008

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Alban Lester
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1 Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring counter? b) a binary counter? Show an example of each. Solution 1: a) To use a ring counter as a clock divider, you preload the flip flops with 1 s and 0 s and connect the output of the counter to the input. The master clock (in this case the 100MHz) is used to clock the flip flops, so the values are just rotated through to the output. Using a ring counter will require 1 flip flop per division. Think of a string of flip flops that are preloaded such that the first flip flop is 1 and the rest are 0. Each time the flip flops are clocked, that 1 gets one step closer to the output. If you have five flip flops, you clock through four 0 s (one per clock cycle) before the output is set to 1 (also for one clock cycle). So: 100MHz/20MHz = 5 5 flip flops required 100MHz/1kHz = 100, k flip flops required 100MHz/1Hz = 100 million 10 8 flip flops required The duty cycle of the divided clock is determined by the preloaded values. To get closer to a 50% duty cycle, preload half the flip flops with 1 s and half with 0 s. (Be sure to put all the 1 s together and all the 0 s together so you don t get extra output transitions.) An example of a clock divider using a ring counter is shown below: b) A binary counter is much more efficient than a ring counter for a clock divider. To see the output of a binary counter, look at a truth table. The least significant bit changes in every row, the next bit changes every other row, the next bit changes every 4 th row, etc, so the n th bit changes every 2 n rows. If each row represents a clock cycle, it is easy to see how the first flip flop outputs f0/2, because it takes two rows (two clock cycles) for the output bit to make two transitions (one clock cycle). Similarly, the 2 nd flip flop outputs f0/4, the third flip flop outputs f0/8, etc. What if we want to divide the input clock by something that is not 2 n? The output of the flip flop stages will no longer be the divided clock output directly. Instead, we Page 1 of 12

2 use the output of the binary counter to count cycles, and feed that into a comparator. If you want to divide the master clock by 5, you set the comparator to count 5 cycles of the master clock, toggle its output, and reset the binary counter. The number of flip flops needed to implement a clock divider using a binary counter is significantly less than the ring counter in part (a). The number of bits needed to represent the clock divisor determines the number of flip flops required: 100MHz/20MHz = 5 5 < bit binary counter 3 flip flops 100MHz/1kHz = 100k 100k < bit binary counter 17 FFs 100MHz/1Hz = < bit binary counter 27 FFs One additional flip flop is required at the output of the comparator to stabilize the output clock. This cleans up the clock so it doesn t change while the combinational logic inside the comparator still busy switching. An example of a clock divider using a binary counter is shown below (refer to lab 2 for the comparator logic): Problem 2: You have a clock with a frequency of 2*f0 and you want a clock with a frequency of f0 and a 50% duty cycle. Design a simple circuit to do this. Does the duty cycle of the output depend on the duty cycle of the input? Solution 2: The simplest way to do this is to use a single D flip flop, and connect the output Q to the input D through an inverter. Q will toggle with each clock cycle, which means that each full cycle of the clock (i.e., each rising edge) results in only half a cycle on Page 2 of 12

Q. Note that the flip flop will have to preloaded, but it doesn t matter if it starts at 1 or 0. The duty cycle of the output is independent of the input, because the flip flop is edge triggered.

The resulting circuit is shown below: Problem 3: Starting with a cross coupled NOR SR latch, use "bubble pushing" to redraw the latch using NAND gates, and show that it turns into a SR latch.

3 Q. Note that the flip flop will have to preloaded, but it doesn t matter if it starts at 1 or 0. The duty cycle of the output is independent of the input, because the flip flop is edge triggered. Each rising edge of the clock toggles the output Q, but the falling edge of the clock has no effect on the flip flop. The resulting circuit is shown below: Problem 3: Starting with a cross coupled NOR SR latch, use "bubble pushing" to redraw the latch using NAND gates, and show that it turns into a SR latch. Carefully label the inputs and outputs. Solution 3: The NOR SR latch is shown in Figure 6.5 of CLD2. Figures show the equivalent gates, and the steps to convert AND/OR logic to NAND gates only. The first step is to recognize that a NOR gate is equivalent to an AND gate with inverted inputs. (This should look very familiar it is DeMorgan s law.) We can prove this by simply drawing the truth table: A B A + B A B So, that turns our NOR into an AND with inverted inputs. To make it a NAND, we have to add an additional inverter after the output. This results in the circuit below: Page 3 of 12

4 We can get rid of the inverters at the inputs of the NAND gates by re labeling the signals appropriately. The inputs R and S are inverted going into the NAND gates because of the bubbles, so we can change the signal labels to R and S and get rid of the bubble at the input. Notice that the output of each NAND gate is inverted before feeding back into the other gate, then inverted again at the input. These cancel each other out and can be removed. Again, take care to keep the labels for Q and Q correct. See the steps of the conversion in the figure below; the circuit now matches the SR latch that was shown in class: Problem 4: How many different functions are there of 4 variables? Solution 4: Any particular function of 4 variables has 2 4 = 16 unique input combinations, so there are 16 rows of the truth table. How many different combinations are there for these 16 output rows? Each row could have a 1 or a 0 in each of the 16 spots, so there are 2 16 different output combinations, thus 2 16 = 65,536 functions of 4 variables. In general, there are 2 2n different functions of n variables. See page 47 in CLD2 for all the functions of 2 variables ( 2 22 = 16). Problem 5: Given the function F(A,B,C,D) = Σm (3,4,5,6,7, 8, 12,13,15) a) draw a Karnaugh map of this function i) list all of the prime implicants ii) list the essential prime implicants b) write down a minimal sum of products formula for the function c) draw an implementation of the function using only NAND gates d) draw a Karnaugh map of the complement of the function, F i) list all of the prime implicants ii) list the essential prime implicants iii) write down a minimal sum of products formula for the function F e) use De Morgan's law on the formula in d iii) to write down a minimal product of sums formula for F Page 4 of 12

Solution 5: a) Each minterm contributes one element of the on set to the K map: m3 = m0011 put a 1 in the box corresponding to ABCD = 0011 m4 = m0100 put a 1 in the box corresponding to ABCD = 0100

i) Prime implicants are implicants (groups of elements of the on set) that cannot be combined with any other implicants to eliminate a literal.

5 Solution 5: a) Each minterm contributes one element of the on set to the K map: m3 = m0011 put a 1 in the box corresponding to ABCD = 0011 m4 = m0100 put a 1 in the box corresponding to ABCD = 0100 etc. The K map for F is shown below, with prime implicants outlined in blue and essential prime implicants outlined in red. i) Prime implicants are implicants (groups of elements of the on set) that cannot be combined with any other implicants to eliminate a literal. The prime implicants of F are: ACD,AB, ACD,BC,BD ii) Essential prime implicants contain elements of the on set that are not included in any other prime implicant. The essential prime implicants of F are: ACD,AB,ACD,BD. In this case, all except one prime implicants are essential. Also notice that in this case, the essential primes give full coverage. b) The minimal SoP form for the function F is obtained from the essential prime implicants, since they give a full cover: F = ACD + AB + ACD + BD c) The SoP implementation is an AND/OR implementation, so we can use the bubble pushing technique from Problem 3 to convert this to NAND gates. The conversion is shown below: Page 5 of 12

d) The K map for F is the opposite of the K map we made for part (a) just swap the 1s and 0s.

several different minimal SoP expressions. Each MUST contain the essential prime implicant, ACD.

One minimal SoP form is: F = ACD + ABC + ABD + ABD e) DeMorgan s law says that X + Y = XY and XY = X + Y.

6 d) The K map for F is the opposite of the K map we made for part (a) just swap the 1s and 0s. i) The prime implicants of F are: ABD, ABC,BCD,BCD, ACD, ABD,ABC ii) There is only one essential prime for F : ACD iii) There are several different minimal SoP expressions. Each MUST contain the essential prime implicant, ACD. Choose other prime implicants that give full coverage. One minimal SoP form is: F = ACD + ABC + ABD + ABD e) DeMorgan s law says that X + Y = XY and XY = X + Y. We start with F, and then complement both sides: F = ACD + ABC + ABD + ABD Apply DeMorgan s to the right side of the equation by complementing each individual term, and replace the OR s with AND s: F = ACD ABC ABD ABD Now apply DeMorgan s to each individual term, which yields the minimum PoS form Page 6 of 12

7 of F: F = (A + C + D) (A + B + C) (A + B + D) (A + B + D) Problem 6: Design a 3 bit counter with one input. When the input is high, the counter counts by 2 (e.g. 3,5,7,1,3...), and when the input is low the counter counts by 3s (e.g. 0,3,6,1,4,7,2,5,0). a) draw the state diagram b) draw the state transition table. c) draw Karnaugh maps for the next state logic d) find both minimal SoP and PoS formulas for the next states. Solution 6: a) State diagram: b) Transition table: Page 7 of 12

8 c) For the 4 variable K maps, we ll define the inputs (A,B,C,D) = (In, CS[2], CS[1], CS[0]). The Next State outputs will be NS[2], NS[1], and NS[0]. The K maps are: Page 8 of 12

d) The minimal SoP and PoS formulas for the next states are found directly from the K maps.

minimal set of prime implicants that fully cover the on set.

the K map. This is because the PoS form contains maxterms, which we found in the truth table where the output of the function was zero.

9 d) The minimal SoP and PoS formulas for the next states are found directly from the K maps. To obtain the minimal SoP form, take the normal approach: identify prime implicants of members of the on set as we did in problem 5, and choose a minimal set of prime implicants that fully cover the on set. We get: NS[2] = BC + ABD + BCD + ABC NS[1] = CD + AC + ACD NS[0] = AD + AD To obtain the minimal PoS form, we use the elements of the off set in the K map. This is because the PoS form contains maxterms, which we found in the truth table where the output of the function was zero. Group the 0 s in the K map the same way you would group the 1 s, finding the largest possible sets. These sets are in the K maps above with green boxes. Each set contributes a sum term, but just like finding the maxterms the variables are complemented. For example, the box of 4 Page 9 of 12

10 0 s in the left two columns of the N[0] K map yield the term A + D (instead of AD as they would if these were 1 s). The resulting PoS forms for the next states are: NS[2] = (B + C) (A + B + D) (B + C + D) (A + B + C) NS[1] = (A + C) (C + D) (A + C + D) NS[0] = (A + D) (A + D) Problem 7: A Gray Code is a binary code with the property that exactly one bit changes from each position to the next. An excellent example of a two bit Gray Code is the header column (or header row) on a 4 bit K Map: 00, 01, 11, 10. Gray Codes occasionally arise in specialized situations. For example, when one is synthesizing a range filter in a router, it turns out that ranges tend to be more compactly represented in a Gray Code representation than in standard binary code. (a) Write down the three bit Gray code sequence starting with 000, (hint: try a 3 bit KMap, then go left to right across the top and then right to left across the bottom, using the row bit as the high order bit and the column bits as the two low order bits. This works; why? (b) draw the state diagram (c) draw the state transition table. (d) draw Karnaugh maps for the next state logic (e) find both minimal SoP and PoS formulas for the next state Solution 7: a) The three bit Gray Code sequence is: 000, 001, 011, 010, 110, 111, 101, 100. Using the three variable K map to find the three bit Gray code works because only one bit changes when you move from one box of the K map to any adjacent box; this is the definition of the Gray Code. Note that this does NOT work if you go left toright across the top row AND left to right across the bottom row; you must move from one cell to the next adjacent cell. b) State diagram: c) State transition table: Page 10 of 12

11 d) K maps: e) Use the same process as we used in Problem 6 to find the minimal SoP and PoS forms for the next states. The minimal SoP forms are: A + = BC + AC Page 11 of 12

12 B + = BC + AC C + = AB + AB The minimal PoS forms are: A + = (A + C) (B + C) B + = (A + C) (B + C) C + = (A + B) (A + B) Page 12 of 12

Odd-Prime Number Detector The table of minterms is represented. Table 13.1

Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1