Synthesis of Combinational Logic

Transcription

1 Synthesis of ombinational Logic 6.4 Gates F = xor Handouts: Lecture Slides, PS3, Lab Spring 2 2/2/ L5 Logic Synthesis

2 Review: K-map Minimization ) opy truth table into K-Map 2) Identify subcubes, selecting the largest available subcube at each step, even if it involves some overlap with previous cubes, until all ones are covered. (Try: 4x4, 2x4 and 4x2, x4 and 4x, 2x2, 2x and x2, finally x) 3) Write down the minimal SOP realization Truth Table The The circled circled terms terms are are called called implicants. implicants. n n implicant implicant not not completely completely contained contained in in another another implicant implicant is is called called a a prime prime implicant. implicant. \ = Spring 2 2/2/ L5 Logic Synthesis 2

3 ase for Non-Minimal SOP = + () () () \ t D = ns t PD = 2nS () NOTE: NOTE: The The steady steady state state behavior behavior of of these these circuits circuits is is identical. identical. They They differ differ in in their their transient transient behavior. behavior. That s what we call a glitch or static hazard = + + If you include equations for all prime implicants, the resulting implementation will be lenient Spring 2 2/2/ L5 Logic Synthesis 3

4 Useful Gate Structures =+ NND-NND Pushing ubbles NOR-NOR =+ xyz = x + y + z x + y = xy Spring 2 2/2/ L5 Logic Synthesis 4

5 More Useful Gate Structures OI (ND-OR-INVERT) V dd D OI (OR-ND-INVERT) D V dd OI and OI structures can be realized using a single MOS gate. However, their function is equivalent to 3 levels of logic. n OI s DeMorgan equivalent is usually easier to think about. D D D Spring 2 2/2/ L5 Logic Synthesis 5

6 i Logic that defies SOP realization S o o Full dder F an simplify the carry out easy enough, eg... o = + + S i S = o = Looks like parity to me ut, the sum, S, doesn t have a simple sum-of-products implementation even though it can be implemented using only two 2-input gates. S / O / Spring 2 2/2/ L5 Logic Synthesis 6

7 Logic synthesis using MUXes Truth Table If is then copy to, otherwise copy to 2-input Multiplexer 4-input Mux implemented as a tree I I I 2 I 3 S S S S S schematic Gate symbol Spring 2 2/2/ L5 Logic Synthesis 7

8 Systematic Implementation of ombinational Logic onsider implementation of some arbitrary oolean function, F(,)... using a MULTIPLEXER as the only circuit element: in out,, in Full-dder arry Out Logic out Spring 2 2/2/ L5 Logic Synthesis 8

9 Small Improvements We can also apply certain optimizations to MUX Logic Full-dder arry Out Logic in out in in, Largely by inspection or exhaustive search out - N-input gate with N- input MUX & one inverter There s something interesting going on in those MUXs Spring 2 2/2/ L5 Logic Synthesis 9

10 General Table Lookup Synthesis Fn(,) MUX Logic Fn(,) Generalizing: In theory, we can build any -output combinational logic block with multiplexers. 2 N For an N-input function we need a input multiplexer. IG Multiplexers? How about -input function? 2-input? Spring 2 2/2/ L5 Logic Synthesis

11 Mux s Guts decoder generates all possible product terms for a set of inputs Decoder Selector Multiplexers 2 3 I I I I can be partitioned into two sections. DEODER that identifies the desired input,and a SELETOR that enables that input onto the output. Hmmm, by sharing the decoder part of the logic MUXs could be adapted to make lookup tables with any number of outputs Spring 2 2/2/ L5 Logic Synthesis

12 New ombinational Device k D D 2 D N DEODER: k SELET inputs, N = 2 k DT OUTPUTs. Selected D j HIGH; all others LOW. Have I mentioned that HIGH is a synonym for and LOW means the same as NOW, we are well on our way to building a general purpose table-lookup device. We can build a 2-dimensional RR of decoders and selectors as follows Spring 2 2/2/ L5 Logic Synthesis 2

13 Shared Decoding Logic There s an extra level of inversion that isn t necessary in the logic. However, it reduces the capacitive load on the module driving this one. in Decoder These are just DeMorgan ized NOR gates S This ROM stores 6 bits in 8 words of 2 bits. out onfigurable Selector We can build a general purpose table-lookup device called a Read-Only Memory (ROM), from which we can implement any truth table and, thus, any combinational device Made from PREWIRED connections, and ONFIGURLE connections that can be either connected or not connected Spring 2 2/2/ L5 Logic Synthesis 3

14 ROM Implementation Details PFET with gate tied to ground = resistor pullup that makes wire unless one of the NFET pulldowns is on. in S out Hardwired ND logic Programmable OR logic dvantages: - Very regular design (can be entirely automated) Problems: - ctive Pull-ups (Static Power) -Long metal runs (Large aps) -Slow JRGON: Inputs to a ROM are called DDRESSES. The decoder s outputs are called WORD LINES, and the outputs lines of the selector are called IT LINES Spring 2 2/2/ L5 Logic Synthesis 4

15 Speeding up ROMS The key making ROMS go fast is to minimize the capacitances of those long wires running through the array. ll of our NOR gates now have exactly 4 inputs in S The best way to accomplish this is to build square arrays. out Why Why NORs? NORs? ouldn t we we eliminate some some inverters by by using using NNDs? Spring 2 2/2/ L5 Logic Synthesis 5

16 Logic ccording to ROMs ROMs ignore the structure of combinational functions... Size, layout, and design are independent of function ny Truth table can be programmed by minor reconfiguration: - Metal layer (masked ROMs) - Fuses (Field-programmable PROMs) - harge on floating gates (EPROMs)... etc. ROMs tend tend to to generate glitchy outputs. WH? Model: LOOK UP value of function in truth table... Inputs: DDRESS of a T.T. entry ROM SIZE = # TT entries for an N-input boolean function, size = Why do ROM SIZES grow by factors of 4? 2 N x #outputs Spring 2 2/2/ L5 Logic Synthesis 6

17 Example: 7-sided Die What nature can t provide electronics can (with the same number of LEDs!). We want to construct a die with the following sides: n array of LEDs, labeled as follows, can be used to display the outcome of the die: T U V W X Z Spring 2 2/2/ L5 Logic Synthesis 7

18 ROM-ased Design Truth Table for a 7-sided Die T U V W X Z Once we ve written out the truth table we ve basically finished the design Possible optimizations: - Eliminate redundant outputs - ddressing tricks T V W U X Z Spring 2 2/2/ L5 Logic Synthesis 8

19 Simple ROM implementation different set of ND gates might make this a lot simpler T/Z U/ V/X W T V W U X No output depends on this product term or WORD LINE T/Z U/ V/X W That was easy but there is clearly some waste. - unused products - over-specified terms Z Spring 2 2/2/ L5 Logic Synthesis 9

20 nother General-Purpose Logic Device This logic is so simple we should just build it with 2 gates! What if the ND terms of a ROM s decoder were programmable in the same way that the OR terms are? Then we could use some of our logic minimization tricks to reduce the size of the ROM array. T/Z = U/ = + V/X = W = T V W U X Z T/Z U/ V/X W PL Programmable Logic rray Spring 2 2/2/ L5 Logic Synthesis 2

21 PL 7-sided Die implementation PLs like ROMs support the synthesis of arbitrary logic functions using SOP implementations. However, they allow for - minimal realizations - smaller (faster) arrays The IT lines of PLs tend to be long and limit their speed T/Z U/ V/X Regular structure - automatic generation - easy design - still slower than optimized gates W One More Trick! T V W U X Z Spring 2 2/2/ L5 Logic Synthesis 2

22 PL Folding Often we can share the same bit line with two outputs Similarly, it is possible to bring inputs into both sides of the array, but then things start to look a lot like a pair of mirrored PLs. T V W U X V/X T/Z Z W U/ Spring 2 2/2/ L5 Logic Synthesis 22

23 PLs: Programmable rray Logic User-programmable NDs Fixed ORs nother approach to structured logic design is Programmable rray Logic (PL). These were once popular offthe-shelf devices. They basically replaced TTL gates in the 8s and fueled the minicomputer revolution. Today, they are practically fossils PLs have a programmable decoder (ND plane) with fixed selector logic (OR plane). These devices were useful for implementing large fan-in gates and SOP logic expressions. They could be purchased as unprogrammed chips and configured in the field using an inexpensive programmer Spring 2 2/2/ L5 Logic Synthesis 23

24 Summary of Logic rrays MUXes ROMs n N-input mux can directly implement an N-input truth tables with -output Shared decoding logic Generates all products an implements truth tables with any number of outputs Easy to specify Regular layout Inefficient use of space/time PLs PLs an achieve minimal SOP realizations Generates only the products needed Relies on minimization for compact designs Regular layout Easily prefabricated and packaged Today it s back to gates Spring 2 2/2/ L5 Logic Synthesis 24

25 Modern Methods: Standard ells First, a library of fixed-pitch logic cells (gates, registers, muxes, adders, I/O pads, ) are created. data sheet for each cell describes its function, area, power, propagation delay, output rise/fall time as function of load, etc. OI.2 Z DREG D Q Spring 2 2/2/ L5 Logic Synthesis 25

26 Standard ell Example H routing: metal3 V routing: metal2 in-cell: metal poly vdd pfets nfets gnd Similar to designing with board level components 2 years ago. D tools place and route cells. - minimize area - meet timing specs In this case, the router needed so much space for running wires that cell rows were pushed apart. In many cases, wiring determines the size of the layout! Spring 2 2/2/ L5 Logic Synthesis 26

27 Fast Turn-around: Gate rrays Gate arrays use fixed arrays of transistors that are personalized in a final processing step that adds wires and contacts. Most popular architecture is Seaof-Gates where the core of the chip is a continuous array of FETs. Routing occurs over the top of unused transistors. metal 2 vertical wiring tracks metal horizontal wiring tracks VDD Pros: - can be prefabricated - only last few masks are customized GND from IEEE JSS, V25, No5, Oct Spring 2 2/2/ L5 Logic Synthesis 27

28 Gate rray Example INV NOR GND The last two layers of metal are used to define the function of the transistors. Side-by-side gates are isolated from one another by turning off the gate of a transistor between them. This is called gateisolation. 3 nfets 3 pfets gate isolation VDD Spring 2 2/2/ L5 Logic Synthesis 28

29 Sum of products Summary Karnaugh maps Use minimal cover of prime implicants to get minimal SOP Use all prime implicants to get lenient (glitch-free) implementation SOP implementation methods NND-NND, NOR-NOR OI and OI for fast low fan-in SOP logic Muxes used to build table-lookup implementations ROMs Decoder logic generates all possible product terms Selector logic determines which p terms are or ed together PLs are ROMs with optimized decoders that generate only the product terms that are needed Spring 2 2/2/ L5 Logic Synthesis 29

30 ombinational Logic Design Finale Now you know everything about combinational logic design. Much combinational logic today is synthesized from high level specifications (equations and truth tables). Next we ll build circuits that can actually remember something! Spring 2 2/2/ L5 Logic Synthesis 3