ECE380 Digital Logic

Transcription

1 ECE38 Digital Logic Optimized Implementation of Logic Functions: Karnaugh Maps and Minimum Sum-of-Product Forms Dr. D. J. Jackson Lecture 7- Karnaugh map The key to finding a minimum cost SOP or POS form is applying the combining property (4a for SOP or 4b for POS) The Karnaugh map (K-map) provides a systematic (and graphical) way of performing this operation Minterms can be combined by 4a when they differ in only one varile f(x,y,z) = xyz+xyz = xy(z+z ) = xy() = xy The K-map illustrates this combination graphically Dr. D. J. Jackson Lecture 7-2

2 Karnaugh map The K-map is an alternative to a truth tle for representing an expression K-map consists of cells that correspond to rows of the truth tle Each cell corresponds to a minterm A two varile truth tle and the corresponding K- map x x 2 f m m m 2 m 3 x 2 x m m m 2 m 3 Dr. D. J. Jackson Lecture 7-3 Karnaugh map x 2 x Values for the first varile are listed across the top m m 2 m m 3 Values for the second varile are listed down the left side Dr. D. J. Jackson Lecture 7-4

3 Karnaugh map groupings Minterms in adjacent squares on the map can be combined since they differ in only one varile Indicated by looping the corresponding s on the map (the s must be adjacent) Looping two s together corresponds to eliminating a term and a varile from the output expression => xy+xy = x x y x y f f=xy +xy=x Dr. D. J. Jackson Lecture 7-5 K-map groupings example x y f y x y x f=x+y Note that the bottom two cells differ in only one varile (x) and the right two cells differ in only one varile (y) Dr. D. J. Jackson Lecture 7-6

4 K-map groupings example Draw the K-map and give the minimized logic expression for the following truth tle. Show the groupings made in the K-map x y f Dr. D. J. Jackson Lecture 7-7 Three varile K-map A three-varile K-map is constructing by laying 2 two-varile maps side by side K-map are always laid out such that adjacent squares only differ by one varile (i.e. by bit in the binary expression of the minterm values) x y z Minterm m =x y z m =x y z m 2 =x yz m 3 =x yz m 4 =xy z m 5 =xy z m 6 =xyz m 7 =xyz z xy m m m 2 m 3 m 6 m 7 m 4 m 5 End cells are adjacent Dr. D. J. Jackson Lecture 7-8

5 Example three-varile K-maps f(x,y,z)=σm(,,2,4) =x y +x z +y z z xy f(x,y,z)=σm(,,2,3,4) =x +y z z xy A grouping of four eliminates 2 variles Dr. D. J. Jackson Lecture 7-9 Guidelines for combining terms Can combine only adjacent s Can group only in powers of 2 (,2,4,8, etc.) Try to form as large a grouping as possible Do not generate more groups than are necessary to cover all the s Dr. D. J. Jackson Lecture 7-

6 Example groupings xy z xy z f=z f=yz +x xy z xy z f=z +y f=y+x z Dr. D. J. Jackson Lecture 7- K-map groupings example Draw the K-map and give the minimized logic expression for the following. f(a,b,c)=σm(,2,3,4,5,6) Show the groupings made in the K-map Dr. D. J. Jackson Lecture 7-2

7 Four varile K-map A four-varile K-map is constructing by laying 2 three-varile maps together to create four rows f(a,b,c,d) cd m m 4 m 2 m 8 m m 5 m 3 m 9 m 3 m 7 m 5 m m 2 m 6 m 4 m Dr. D. J. Jackson Lecture 7-3 Four varile K-map Adjacencies wrap around in the K-map cd m m 4 m 2 m 8 m m 5 m 3 m 9 m 3 m 7 m 5 m m 2 m 6 m 4 m Dr. D. J. Jackson Lecture 7-4

8 Example four-varile K-maps f(a,b,c,d)=σm(2,3,9-,3) =ac d+b c cd f(a,b,c,d)=σm(3-7,9,,2-5) =b+cd+ad cd Dr. D. J. Jackson Lecture 7-5 Example groupings cd cd f(a,b,c,d)=b +d f(a,b,c,d)=b d+bd Dr. D. J. Jackson Lecture 7-6

9 Example groupings cd cd f(a,b,c,d)=b d +bd f(a,b,c,d)=b d+bd +a b Dr. D. J. Jackson Lecture 7-7

10 ECE38 Digital Logic Optimized Implementation of Logic Functions: Strategy for Minimization, Minimum Product-of-Sums Forms, Incompletely Specified Functions Dr. D. J. Jackson Lecture 8- Terminology For a given term, each appearance of a varile (in true or complemented form) is called a literal xyz => three literals c d => four literals Any or group of s that can be combined on a K- map represents an implicant of a function An implicant is a prime implicant if it cannot be combined with another implicant to remove a varile A collection of implicants that account of all valuations for which a given function is is called a cover of that function Cost is the number of gates plus the total number of inputs to all gates in the circuit Dr. D. J. Jackson Lecture 8-2

11 Terminology example cd f(a,b,c,d)=σm(,,4,5,7,9,) Example Implicants: all single s, a c, a b c, a bd, d Prime Implicants: a c, a bd, d, b c d f(a,b,c,d) min : a c +a bd+ d Thus, a minimum SOP form contains only (but not necessarily all) prime implicants. Dr. D. J. Jackson Lecture 8-3 Prime implicants distinctions Essential: needed to form a minimum solution Nonessential: not necessarily needed to form a minimum solution cd All prime implicants: b d, a bc, c a c d, acd Essential primes: b d, a bc, c Nonessential primes: a c d, acd f(a,b,c,d) min : b d+a bc +c Minimum contains all essential and possibly some nonessential primes Dr. D. J. Jackson Lecture 8-4

12 Prime implicants example cd Essential primes: a c, ac d Nonessential primes: a bd, bc d One of these must be included to form a minimum solution f(a,b,c,d) min : a c+ac d+ a bd bc d Dr. D. J. Jackson Lecture 8-5 Prime implicants example Identify all prime implicants for the given truth tle. Which are essential and which are nonessential? What is a minimum SOP expression for this function? cd Dr. D. J. Jackson Lecture 8-6

13 Minimization of POS expressions POS minimization using K-maps proceeds exactly as does SOP form except that groupings of s in the K-map are used to form POS terms. K-map can be constructed directly from ΠM expression for a function Place s in the K-map for every maxterm in the ΠM expression Dr. D. J. Jackson Lecture 8-7 Minimization of POS example f(a,b,c)=(a+b +c )(a +b+c )(a +b +c)(a +b +c ) f(a,b,c)=πm(3,5,6,7) c f=(a +b )(b +c )(a +c ) Dr. D. J. Jackson Lecture 8-8

14 Minimization of POS example f(a,b,c,d)=πm(,,4,8,-2,4,5) cd (c+d) (a+b+c) (a +c ) f(a,b,c,d) min = (a+b+c)(a +c )(c+d) Dr. D. J. Jackson Lecture 8-9 K-map groupings example Draw the K-map and give the minimized POS logic expression for the following. f(a,b,c)=πm(,2,3,5-7) Show the groupings made in the K-map Dr. D. J. Jackson Lecture 8-

15 Incompletely specified functions In digital systems it often happens that some input conditions (i.e. some input valuations) can never happen An input combination that can never happen is referred to as a don t care condition As a circuit is designed, a don t care condition can be ignored (i.e. the output for that condition can be treated as or in the truth tle) A function that has don t care condition(s) is said to be incompletely specified Dr. D. J. Jackson Lecture 8- Example function with don t cares x y z f d d Assume for a three varile function f(x,y,z) that the input combination xy= never occurs, otherwise the function is Σm(,,4,5) f(x,y,z)= Σm(,,4,5)+D(2,3) Or f(x,y,z)= ΠM(6,7) D(2,3) Dr. D. J. Jackson Lecture 8-2

16 Example function with don t cares f(x,y,z)= Σm(,,4,5)+D(2,3) f(x,y,z)= ΠM(6,7) D(2,3) xy z d xy z d d d f(x,y,z)= y f(x,y,z)= y Dr. D. J. Jackson Lecture 8-3 Minimum SOP form. Choose a minterm (a in the K-map) which is not yet covered (don t consider d s). 2. Find all adjacent s and d s (check the n adjacent cells for an n-varile K-map). 3. If a single term (i.e. a single looping) covers the and all adjacent s and d s then the looping forms an essential prime implicant. Loop the essential prime. 4. Repeat steps -3 until all essential prime implicants are located. 5. Find a minimum set of nonessential prime implicants to cover (loop) the remaining s. If more than set is possible, choose the set with the minimum number of literals (the largest grouping). Dr. D. J. Jackson Lecture 8-4

17 Minimum POS form. Choose a maxterm (a in the K-map) which is not yet covered (don t consider d s). 2. Find all adjacent s and d s (check the n adjacent cells for an n-varile K-map). 3. If a single term (i.e. a single looping) covers the and all adjacent s and d s then the looping forms an essential prime implicant. Loop the essential prime. 4. Repeat steps -3 until all essential prime implicants are located. 5. Find a minimum set of nonessential prime implicants to cover (loop) the remaining s. If more than set is possible, choose the set with the minimum number of literals (the largest grouping). Dr. D. J. Jackson Lecture 8-5

18 ECE38 Digital Logic Optimized Implementation of Logic Functions: Multiple Output Circuits, NAND and NOR Logic Networks Dr. D. J. Jackson Lecture 9- Multiple output circuits In all previous examples we have considered only single output functions In practice, these functions may be part of some larger circuit that has many such functions Circuits that implement these functions may be combined into a less costly single circuit with multiple outputs by sharing some gates needed in the implementation of the single functions Dr. D. J. Jackson Lecture 9-2

19 Multiple output circuit example cd cd f (a,b,c,d)=ac +a c+bc d cost=4 gates+ inputs f 2 (a,b,c,d)=ac +a c+bcd cost=4 gates+ inputs NOTE: cost ignores NOT gates Dr. D. J. Jackson Lecture 9-3 Multiple output circuit example b c d a c a c b c d f f 2 cost=6 gates+6 inputs Dr. D. J. Jackson Lecture 9-4

20 Multiple output circuit example In this case, the minimum combined circuit was derived from the minimum circuit for each function (f and f 2 ) This will not always be the case. Consider two functions f 3 and f 4. cd cd Optimal realization of f 3 Optimal realization of f 4 Dr. D. J. Jackson Lecture 9-5 Multiple output circuit example cd cd Optimal realization of f 3 and f 4 together Dr. D. J. Jackson Lecture 9-6

21 NAND and NOR logic networks A NAND gate is a functional combination of an AND gate followed by a NOT gate A NOR gate is a functional combination of an OR gate followed by a NOT gate x x 2 x x 2 x x 2 x + x 2 Dr. D. J. Jackson Lecture 9-7 DeMorgan s theorem in gate terms () =a +b (a+b) =a b Dr. D. J. Jackson Lecture 9-8

22 AND-OR and NAND-NAND networks If we have a network in AND-OR (SOP) form, we can convert it to a NAND-NAND network Dr. D. J. Jackson Lecture 9-9 OR-AND and NOR-NOR networks If we have a network in OR-AND (POS) form, we can convert it to a NOR-NOR network Dr. D. J. Jackson Lecture 9-

23 ECE38 Digital Logic Implementation Technology: Standard Chips and Programmle Logic Devices Dr. D. J. Jackson Lecture - Standard chips A number of chips, each with a few logic gates, are commonly used for small logic circuits These are known as 74-series devices because the part numbers always begin with the number 74 Commonly packaged in a dual-inline package (DIP) Chips external connections are called pins or leads Two pins connect V DD and GND to supply power for the chip. Dr. D. J. Jackson Lecture -2

24 A 74-series chip pin 4 V DD Gnd Dual-inline package Structure of 744 chip pin pin 7 Dr. D. J. Jackson Lecture -3 Implementation of f=+b c Vdd a b c Gnd f Dr. D. J. Jackson Lecture -4

25 74-series chips For each specific 74-series chip, a number of variants are fricated with differing technologies For example: The 74LS is built with a technology called transistor-transistor logic (TTL) The 74HC is fricated using CMOS technology Most popular chips in use today are the CMOS variants Dr. D. J. Jackson Lecture -5 Programmle logic devices The function provided by each 74-series device is fixed and each chip only provides a few logic gates These limitations make use of these chips inefficient for building large circuits It is possible to fricate chips with a large amount of circuitry (gates) but with a structure (interconnection) that is not fixed Called programmle logic devices (PLDs) Dr. D. J. Jackson Lecture -6

26 Programmle logic devices A PLD is a general purpose chip for implementing logic circuitry Contains a collection of logic circuit elements that can be customized in different ways Can be viewed as a black box containing logic gates and programmle switches that allow for different connections between the logic elements Can implement whatever logic circuit is needed subject to limitations of the device inputs (logic variles) Logic gates and programmle switches outputs (logic functions) Dr. D. J. Jackson Lecture -7 Programmle Logic Array (PLA) The first PLD developed was the programmle logic array (PLA) Based on the premise that any function can be written in SOP form, a PLA consists of Input buffers and inverters that provide the true and complement form for each input varile A collection of AND gates, with inputs that are selectle (programmle) A collection of OR gates, with inputs that are selectle (programmle) X Input buffers and inverters AND plane Xn X X Xn Xn P Pk f OR plane fm Dr. D. J. Jackson Lecture -8

27 Gate-level diagram of a PLA x x 2 x 3 Programmle connections P OR plane P 2 P 3 P 4 AND plane f f 2 Dr. D. J. Jackson Lecture -9 Customary schematic of a PLA x x 2 x 3 P OR plane f =x x 2 +x x 3 + x x 2 x 3 f 2 =x x 2 +x x 2 x 3 +x x 3 P 2 P 3 P 4 AND plane f f 2 Dr. D. J. Jackson Lecture -

28 Programmle Array Logic (PAL) In a PLA both the AND and the OR planes are programmle A simpler device with a fixed OR plane is called a programmle array logic (PAL) device As PALs are easier to manufacture and can operate faster than a PLA, most practical applications using these small programmle devices use the PAL structure Dr. D. J. Jackson Lecture - An example of a PAL x x x 2 3 P P 2 f P 3 P 4 f 2 AND plane Dr. D. J. Jackson Lecture -2

29 Extra circuitry in a PAL Most actual PAL devices include extra circuitry at the output of each OR gate to provide additional functionality The term macrocell refers to the OR gate combined with the extra circuitry Select Enle Flip-flop D Q f Clock To AND plane Dr. D. J. Jackson Lecture -3 Complex Programmle Logic Devices (CPLDs) For larger designs that single PLAs or PALs cannot accommodate, a complex programmle logic device (CPLD) can be utilized A CPLD consists of multiple circuit blocks with internal wiring to connect the blocks together and to the pins on the chip Each circuit block is similar to a PAL PAL-like blocks Commercial CPLDs have from 2 to more than PAL-like blocks, with 6 macrocells in each block Each macrocell is the equivalent of approximately 2 gates About 2, equivalent gates in a CPLD of macrocells Can construct moderately large logic circuits in a single chip Dr. D. J. Jackson Lecture -4

30 Structure of a CPLD I/O block I/O block PAL-like block Interconnection wires PAL-like block PAL-like block PAL-like block I/O block I/O block Dr. D. J. Jackson Lecture -5 Field Programmle Gate Arrays To implement even larger circuits, it is convenient to use a different chip that has an even larger logic capacity A field programmle gate array (FPGA) Does not contain AND and OR planes Instead provides an array of logic blocks and interconnection wires between the logic blocks Interconnection wires are arranged in horizontal and vertical routing channels containing wires are programmle switches Caple of implementing logic functions of millions of equivalent gates Dr. D. J. Jackson Lecture -6

31 Structure of an FPGA Logic block Interconnection switches I/O block I/O block I/O block I/O block Dr. D. J. Jackson Lecture -7