Digital Circuits Introduction

Transcription

1 Lecture #6 OUTLINE Logic inary representations Combinatorial logic circuits Chap Reading EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu Digital Circuits Introduction nalog: signal amplitude is continuous with time. Digital: signal amplitude is represented by a restricted set of discrete numbers. inary: only two values are allowed to represent the signal: High or low (i.e. logic or ). Digital word: Each binary digit is called a bit series of bits form a word yte is a word consisting of 8-bits dvantages of digital signal Digital signal is more resilient to noise can more easily differentiate high () and low () Transmission Parallel transmission over a bus containing n wires. aster but short distance (internal to a computer or chip) Serial transmission (transmit bits sequentially) Longer distance EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 2

2 inary Representation N bit can represent 2 N values: typically from to 2 N - 3-bit word can represent 8 values: e.g.,, 2, 3, 4, 5, 6, 7 Conversion Integer to binary raction to binary (3.5 =. 2 and.392 =. 2 ) Octal and hexadecimal EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 3 Logic Gates and Memories Logic gates Combine several logic variable inputs to produce a logic variable output Memory Memoryless: output at a given instant depends the input values of that instant. Momory: output depends on previous and present input values. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 4 2

3 oolean algebras are algebraic structures which "capture the essence" of the logical operations ND, OR and NOT as well as the corresponding set theoretic operations intersection, union and complement. They are named after George oole, an English mathematician at University College Cork, who first defined them as part of a system of logic in the mid 9th century. Specifically, oolean algebra was an attempt to use algebraic techniques to deal with expressions in the propositional calculus. Today, oolean algebras find many applications in electronic design. They were first applied to switching by Claude Shannon in the 2th century. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 5 oolean algebras The operators of oolean algebra may be represented in various ways. Often they are simply written as ND, OR and NOT. In describing circuits, NND (NOT ND), NOR (NOT OR) and XOR (exclusive OR) may also be used. Mathematicians often use for OR and for ND (since in some ways those operations are analogous to addition and multiplication in other algebraic structures) and represent NOT by a line drawn above the expression being negated. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 6 3

4 oolean lgebra NOT operation (inverter) g = = ND operation g = g = g= g = g ( g) gc = g( gc) OR operation = = = = ( ) C = ( C) EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 7 Graphic Representation g = = ull square = complete set = Yellow part = NOT() = White circle = EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 8 4

5 Graphic Representation = = ( ) g( ) = g Exclusive OR=yellow and blue part intersection/overlap part =exactly when only one of the input is true EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 9 oolean lgebra Distributive Property g( C) = g gc ( ) gc = ( ) g( C) De Morgan s laws = g g = n excellent web site to visit EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 5

6 Examples = C C (CD) (DE) = C (DE) D E EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu Logic unctions, Symbols, & Notation TRUTH NME SYMOL NOTTION TLE NOT = OR = ND = EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 2 6

7 7 EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 3 Logic unctions, Symbols, & Notation 2 NOR = NND = XOR (exclusive OR) = EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 4 Circuit Realization ( ) ( ) = = = g g

8 an in/an out Complex digital operations are formed with a variety of gates interconnected to yield the desired logic function. Sometimes a number of inputs are connected to one gate input and output of a gate may be connected to a number of gates. an-in: the maximum number of logic gates that can be connected at the input of a gate without altering its performance. an-out: the maximum number of logic gates that can be connected to the output of a gate without altering its performance. Typical fan-in and fan-out numbers are 3. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 5 Inverter = NOT Gate V in V out Ideal Transfer Characteristics V out V/2 V V in EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 6 8

9 NMOS Resistor Pull-Up Circuit: Voltage-Transfer Characteristic v OUT R D i D v IN i D v DS = v OUT v IN = V T v IN /R D v GS = v in V T increasing v GS = v IN > V T v DS EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 7 Disadvantages of NMOS Logic Gates Large values of R D are required in order to achieve a low value of V OL keep power consumption low Large resistors are needed, but these take up a lot of space. One solution is to replace the resistor with an NMOSET that is always on. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 8 9

10 The CMOS Inverter: Intuitive Perspective CIRCUIT SWITCH MODELS G S D R p D V OL = V V OH = G S R n Low static power consumption, since one MOSET is always off in steady state = = V EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 9 CMOS Inverter Voltage Transfer Characteristic N: sat P: sat N: off P: lin C G S D N: sat P: lin D E G D S N: lin P: sat N: lin P: off EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 2

11 CMOS Inverter Load-Line nalysis = V GSp V GSp = - I Dn =-I Dp = V DSp increasing = V = V DSp = - I Dn =-I Dp increasing V DSp = - V DSp = =V DSn EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 2 CMOS Inverter Load-Line nalysis: Region V Tn I Dn =-I Dp V GSp = - V DSp = - I Dn =-I Dp =V DSn EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 22

12 CMOS Inverter Load-Line nalysis: Region V DD /2 > > V Tn V GSp = - I Dn =-I Dp V DSp = - I Dn =-I Dp =V DSn EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 23 CMOS Inverter Load-Line nalysis: Region D V DD V Tp > > /2 V GSp = - I Dn =-I Dp V DSp = - I Dn =-I Dp =V DSn EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 24 2

13 CMOS Inverter Load-Line nalysis: Region E V IN > V Tp V GSp = - I Dn =-I Dp V DSp = - I Dn =-I Dp =V DSn EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 25 eatures of CMOS Digital Circuits The output is always connected to or GND in steady state ull logic swing; large noise margins Logic levels are not dependent upon the relative sizes of the devices ( ratioless ) There is no direct path between and GND in steady state no static power dissipation EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 26 3

14 The CMOS Inverter: Current low during Switching N: sat P: sat i N: off P: lin C G i S D D N: sat P: lin D E G S N: lin P: sat N: lin P: off EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 27 Power Dissipation due to Direct-Path Current G S v IN : -V T v IN i D v OUT V T D I peak G S i: t sc time Energy consumed per switching period: E = t dp sc V DD I peak EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 28 4

15 NMOS NND Gate Output is low only if both inputs are high R D Truth Table EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 29 NMOS NOR Gate Output is low if either input is high R D Truth Table EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 3 5

16 N-Channel MOSET Operation n NMOSET is a closed switch when the input is high X Y X Y Y = X if and Y = X if or NMOSETs pass a strong but a weak EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 3 P-Channel MOSET Operation PMOSET is a closed switch when the input is low X Y X Y Y = X if and = ( ) Y = X if or = () PMOSETs pass a strong but a weak EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 32 6

17 Pull-Down and Pull-Up Devices In CMOS logic gates, NMOSETs are used to connect the output to GND, whereas PMOSETs are used to connect the output to. n NMOSET functions as a pull-down device when it is turned on (gate voltage = ) PMOSET functions as a pull-up device when it is turned on (gate voltage = GND) input signals 2 N 2 N Pull-up network Pull-down network PMOSETs only (, 2,, N ) NMOSETs only EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 33 CMOS NND Gate EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 34 7

18 CMOS NOR Gate EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 35 CMOS Pass Gate X Y Y = X if EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 36 8

19 Combinational Logic Circuits Logic gates combine several logic-variable inputs to produce a logic-variable output. Combinational logic circuits are memoryless because their output value at a given instant depends only on the input values at that instant. Next time, we will study sequential logic circuits that possess memory because their present output value depends on previous as well as present input values. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 37 Logical Sufficiency of NND Gates If the inputs to a NND gate are tied together, an inverter results rom De Morgan s laws, the OR operation can be realized by inverting the input variables and combining the results in a NND gate. Since the basic logic functions (ND, OR, and NOT) can be realized by using only NND gates, NND gates are sufficient to realize any combinational logic function. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 38 9

20 Logical Sufficiency of NOR Gates Show how to realize the ND, OR, and NOT functions using only NOR gates Since the basic logic functions (ND, OR, and NOT) can be realized by using only NOR gates, NOR gates are sufficient to realize any combinational logic function. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 39 Synthesis of Logic Circuits Suppose we are given a truth table for a logic function. Is there a method to implement the logic function using basic logic gates? nswer: There are lots of ways, but one simple way is the sum of products implementation method: ) Write the sum of products expression based on the truth table for the logic function 2) Implement this expression using standard logic gates. We may not get the most efficient implementation this way, but we can simplify the circuit afterwards EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 4 2

21 Logic Synthesis Example: dder Input C Output S S S using sum-of-products: ) ind where S is 2) Write down each product of inputs which create a C C C C 3) Sum all of the products C C C C 4) Draw the logic circuit EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 4 NND Gate Implementation De Morgan s law tells us that is the same as y definition, is the same as ll sum-of-products expressions can be implemented with only NND gates. EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 42 2

22 Creating a etter Circuit What makes a digital circuit better? ewer number of gates ewer inputs on each gate multi-input gates are slower Let s see how we can simplify the sum-ofproducts expression for S, to make a better circuit Use the oolean algebra relations EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 43 Karnaugh Maps Graphical approach to minimizing the number of terms in a logic expression:. Map the truth table into a Karnaugh map (see below) 2. or each, circle the biggest block that includes that 3. Write the product that corresponds to that block. 4. Sum all of the products 2-variable Karnaugh Map 3-variable Karnaugh Map C 4-variable Karnaugh Map CD EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 44 22

23 Karnaugh Map Example Input C Output S S Simplification of expression for S : EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 45 C C C C S = C C urther Comments on Karnaugh Maps The algebraic manipulations needed to simplify a given expression are not always obvious. Karnaugh maps make it easier to minimize the number of terms in a logic expression. Terminology: 2-cube: 2 squares that have a common edge (-> product of 3 variables) 4-cube: 4 squares with common edges (-> product of 2 variables) In locating cubes on a Karnaugh map, the map should be considered to fold around from top to bottom, and from left to right. Squares on the right-hand side are considered to be adjacent to those on the left-hand side. Squares on the top of the map are considered to be adjacent to those on the bottom. Example: The four squares in the map corners form a 4-cube CD EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu 46 23