VLSI Logic Structures

Transcription

1 VLSI Logic Structures Ratioed Logic Pass-Transistor Logic Dynamic CMOS Domino Logic Zipper CMOS Spring 25 John. Chandy

2 inary Multiplication + x Multiplicand Multiplier Partial products Result Spring 25 John. Chandy

3 Wallace-Tree Multiplier Partial products First stage it position (a) (b) Second stage Final adder F (c) H (d) Spring 25 John. Chandy

4 Wallace-Tree Multiplier Partial products x 3 y 3 x 3 y 2 x 2 y 2 x 3 y x y 2 x 3 y x y x 2 y x y x 2 y 3 x y 3 x y 3 x y 2 x y x First stage H H Second stage F F F F Final adder z 7 z 6 z 5 z 4 z 3 z 2 z z Spring 25 John. Chandy

5 Ratioed Logic V DD V DD V DD Resistive Load R L Depletion Load V T < PMOS Load F F V SS F In In 2 In 3 PDN In In 2 In 3 PDN In In 2 In 3 PDN V SS V SS V SS (a) resistive load (b) depletion load NMOS (c) pseudo-nmos Goal: to reduce the number of devices over complementary CMOS Spring 25 John. Chandy

6 Ratioed Logic V DD Resistive Load R L N transistors + Load V OH = V DD F V OL = R PN R PN + R L In In 2 In 3 PDN ssymetrical response Static power consumption V SS t pl =.69 R L C L Spring 25 John. Chandy

7 ctive Loads V DD V DD Depletion Load V T < PMOS Load F V SS F In In 2 In 3 PDN In In 2 In 3 PDN V SS V SS depletion load NMOS pseudo-nmos Spring 25 John. Chandy

8 Pseudo-NMOS VTC W/L p = 4 V out [V].5. W/L p = 2.5 W/L p =.5 W/L p =.25 W/L p = V in [V] Spring 25 John. Chandy

9 Improved Loads V DD Enable M M2 M >> M2 F C D C L daptive Load Spring 25 John. Chandy

10 Improved Loads (2) V DD V DD M M2 Out Out PDN PDN2 V SS V SS Differential Cascode Voltage Switch Logic (DCVSL) Spring 25 John. Chandy

11 DCVSL Example Out Out XOR-NXOR gate Spring 25 John. Chandy

12 Pass-Transistor Logic Transmission Gate ased OUT Z OUT Z Spring 25 John. Chandy

13 Example: ND Gate F = Spring 25 John. Chandy

14 NMOS-Only Logic V DD In x.5µm/.25µm.5µm/.25µm.5µm/.25µm Out Voltage [V] Out x In Time [ns] Spring 25 John. Chandy

15 Complementary Pass Transistor Logic Pass-Transistor Network F (a) Inverse Pass-Transistor Network F F= F=+ F= ΒY (b) F= F=+ F= ΒY ND/NND Spring 25 OR/NOR EXOR/NEXOR John. Chandy

16 Resistance of Transmission Gate Fig. 7.35, CMOS Digital Integrated Circuits, Kang and Leblebici Spring 25 John. Chandy

17 Pass-Transistor ased Multiplexer S S V DD S V DD M 2 S F M S GND In S S In 2 Spring 25 John. Chandy

18 Pass-Transistor Logic XOR OUT OUT Spring 25 John. Chandy

19 Pass-Transistor Logic Use Karnaugh Map C ND Spring 25 John. Chandy

20 Pass-Transistor Logic C OUT= C 2 transistors vs. 8 transistors C Spring 25 John. Chandy

21 Pass-Transistor Logic C C OUT= C+C 6 transistors vs. 6 transistors C Spring 25 John. Chandy

22 Pass-Transistor Logic C C OUT= C+C 4 transistors vs. 6 transistors C Spring 25 John. Chandy

23 Pass-Transistor Logic C C C OUT= C+C 2 transistors vs. 6 transistors Spring 25 John. Chandy

24 Pass-Transistor Logic OUT Cross Coupled XOR Spring 25 John. Chandy

25 Pass-Transistor Logic In many cases, uses fewer transistors Can be difficult to design Usually requires complemented versions of all signals Difficult to layout Delay analysis is not as well defined in terms of sizing choices Spring 25 John. Chandy

26 Pass-Transistor Logic Delay characteristics nmos-only pass logic has fast fall times Complementary designs have faster rise times, but increasing the pmos width to decrease the rise time will increase the fall time Transmission gate looks like a RC line Spring 25 John. Chandy

27 Next Class Sequential Design Memory and Control Chapter 7 Have a great Spring reak! Spring 25 John. Chandy