VLSI Design. Static CMOS Logic

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1 VLSI esign Static MOS Logic [dapted from Rabaey s igital Integrated ircuits, 2002, J. Rabaey et al.] EE4121 Static MOS Logic.1 ZLM

2 Review: MOS Process at a Glance efine active areas Etch and fill trenches Implant well regions eposit and pattern polysilicon layer Implant source and drain regions and substrate contacts One full photolithography sequence per layer (mask) uilt (roughly) from the bottom up 4 metal 2 polysilicon exception! 3 source and drain diffusions 1 tubs (aka wells, active areas) reate contact and via windows eposit and pattern metal layers EE4121 Static MOS Logic.2 ZLM

3 MOS ircuit Styles Static complementary MOS - except during switching, output connected to either V or GN via a lowresistance path high noise margins - full rail to rail swing - V OH and V OL are at V and GN, respectively low output impedance, high input impedance no steady state path between V and GN (no static power consumption) delay a function of load capacitance and transistor resistance comparable rise and fall times (under the appropriate transistor sizing conditions) ynamic MOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes simpler, faster gates increased sensitivity to noise EE4121 Static MOS Logic.3 ZLM

4 Static omplementary MOS Pull-up network (PUN) and pull-down network (PN) In 1 In 2 In N In 1 In 2 In N V PUN PN PMOS transistors only pull-up: make a connection from V to F when F(In 1,In 2, In N ) = 1 F(In 1,In 2, In N ) pull-down: make a connection from F to GN when F(In 1,In 2, In N ) = 0 NMOS transistors only PUN and PN are dual logic networks EE4121 Static MOS Logic.4 ZLM

5 Threshold rops PUN V S V V 0 V V GS S 0 V -V Tn L L PN V 0 V V Tp V L V GS S L S EE4121 Static MOS Logic.6 ZLM

6 onstruction of PN NMOS devices in series implement a NN function NMOS devices in parallel implement a NOR function + EE4121 Static MOS Logic.7 ZLM

7 ual PUN and PN PUN and PN are dual networks emorgan s theorems + = [!( + ) =!! or!( ) =! &!] = + [!( ) =! +! or!( & ) =!!] a parallel connection of transistors in the PUN corresponds to a series connection of the PN omplementary gate is naturally inverting (NN, NOR, OI, OI) Number of transistors for an N-input logic gate is 2N EE4121 Static MOS Logic.8 ZLM

8 MOS NN F EE4121 Static MOS Logic.9 ZLM

9 MOS NOR + F EE4121 Static MOS Logic.10 ZLM

10 omplex MOS Gate OUT =!( + ( + )) EE4121 Static MOS Logic.12 ZLM

11 Standard ell Layout Methodology Routing channel V signals GN What logic function is this? EE4121 Static MOS Logic.13 ZLM

12 OI21 Logic Graph j X PUN X =!( ( + )) X i V i j GN PN EE4121 Static MOS Logic.14 ZLM

13 Two Stick Layouts of!( ( + )) V V X X GN GN uninterrupted diffusion strip EE4121 Static MOS Logic.15 ZLM

14 onsistent Euler Path n uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph Euler path: a path through all nodes in the graph such that each edge is visited once and only once. X X i V j GN For a single poly strip for every input signal, the Euler paths in the PUN and PN must be consistent (the same) EE4121 Static MOS Logic.17 ZLM

15 OI22 Logic Graph X PUN X =!((+) (+)) X V GN PN EE4121 Static MOS Logic.18 ZLM

16 OI22 Layout V X GN Some functions have no consistent Euler path like x =!(a + bc + de) (but x =!(bc + a + de) does!) EE4121 Static MOS Logic.19 ZLM

17 Stick iagrams ontains no dimensions Represents relative positions of transistors Inverter V NN2 V Out Out GN In GN EE4121 Static MOS Logic.20 ZLM

18 OI22 Logic Graph X PUN X = (+) (+) X V GN PN EE4121 Static MOS Logic.21 ZLM

19 Example: x = ab+cd EE4121 Static MOS Logic.22 ZLM

20 XNOR/XOR Implementation XNOR XOR How many transistors in each? an you create the stick transistor layout for the lower left circuit? EE4121 Static MOS Logic.23 ZLM

21 EE4121 Static MOS Logic.24 ZLM

22 EE4121 Static MOS Logic.25 ZLM

23 simple method for finding the optimum gate ordering is the Euler-path method: Simply find a Euler path in the pull-down network graph and a Euler path in the pull-up network graph with the identical ordering of input labels, i.e., find a common Euler path for both graphs. The Euler path is defined as an uninterrupted path that traverses each edge (branch) of the graph exactly once. Figure 3.12 shows the construction of a common Euler path for both graphs in our example. EE4121 Static MOS Logic.26 ZLM

24 EE4121 Static MOS Logic.27 ZLM

25 VT is ata-ependent M 3 M 4 F= V GS2 = V V S1 V GS1 = V M 2 S M 1 S int weaker PUN 0.5μ/0.25μ NMOS 0.75μ /0.25μ PMOS 0 1 2,: 0 -> 1 =1, :0 -> 1 =1, :0->1 The threshold voltage of M 2 is higher than M 1 due to the body effect (γ) V Tn1 = V Tn0 V Tn2 = V Tn0 + γ( ( 2φ F + V int ) - 2φ F ) since V S of M 2 is not zero (when V = 0) due to the presence of int EE4121 Static MOS Logic.28 ZLM

26 Static MOS Full dder ircuit! out =! in & (!!) (! &!)!Sum = out & (!!! in ) (! &! &! in ) in in! out!sum in in in out = in & ( ) ( & ) Sum =! out & ( in ) ( & & in ) EE4121 Static MOS Logic.30 ZLM

27 Next Time: Pass Transistor ircuits EE4121 Static MOS Logic.31 ZLM

28 Next Lecture and Reminders Next lecture Pass transistor logic - Reading assignment Rabaey, et al, EE4121 Static MOS Logic.32 ZLM