CS8803: Advanced Digital Design for Embedded Hardware
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1 HPTER II-6 MO MO WITHE WITH NETWORK -WITHE IN ERIE -WITHE IN PRLLEL -INPUT ELETOR 883: dvanced Digital Design for Embedded Hardware Lecture : MO Transistors and Layout The idea is to use the series and parallel switch configurations to route signals in a desired fashion. Unfortunately, it is difficult to implement an ideal switch as given. omplementary Metal Oxide emiconductor (MO) devices give us some interesting components. IDEL WITH nmo transistor pmo transistor INPUT DRIN OURE Instructor: ung Kyu Lim (limsk@ece.gatech.edu) WITH GTE GTE Website: OUTPUT OURE DRIN R.M. Dansereau; v.. HPTER II-7 MO TRNFER HRTERITI WITH NETWORK MO -MO WITHE HPTER II-8 MO TRNMIION GTE () WITH NETWORK MO -MO WITHE -TRNFER HR. nmo WITH OPEN LOED nmo when LOED Transmits logic level well Transmits logic level poorly IDEL WITH INPUT OUTPUT MO TRNMIION GTE (WITH) INPUT OUTPUT pmo WITH LOED OPEN pmo when LOED Transmits logic level well Transmits logic level poorly nmo OFF ON pmo OFF ON OUTPUT INPUT INPUT OUTPUT R.M. Dansereau; v.. R.M. Dansereau; v..
2 HPTER II-9 MO TRNMIION GTE (2) MO -MO WITHE -TRNFER HR. -TRNMIION GTE HPTER II- WITH NETWORK HIGH IMPEDNE () MO -MO WITHE -TRNFER HR. -TRNMIION GTE PLIT OF URRENT RO TRNMIION GTE FOR LOGI- ND LOGI- INPUT LOGI- T INPUT LOGI- T INPUT With switches, we can consider three states for an output: Logic- Logic- High Impedance = = = = Path exists for Logic- and Logic- when the switch is LOED. / OUTPUT = / High impedance is a state where the switch is OPEN. / OUTPUT = R.M. Dansereau; v.. R.M. Dansereau; v.. HPTER II- WITH NETWORK HIGH IMPEDNE (2) MO WITH NETWORK -HIGH IMPEDNE HPTER II-2 WITH NETWORK INVERTER (NOT) MO WITH NETWORK -HIGH IMPEDNE nother way of thinking of switches is as follows Path exists for Logic- and Logic- when the switch is LOED, meaning that the impedance/resistance is small enough to allow amply flow of current. OURE = LOED DRIN OURE «KΩ DRIN High impedance is a state where the switch is OPEN, meaning that the impedance/resistance is very large allowing nearly no current flow. PULL-DOWN PULL-UP = OURE = OPEN DRIN OURE» MΩ DRIN This network inverts the binary input value. R.M. Dansereau; v.. R.M. Dansereau; v..
3 HPTER II-3 WITH NETWORK NND NETWORK MO WITH NETWORK -HIGH IMPEDNE -INVERTER HPTER II-4 WITH NETWORK NOR NETWORK WITH NETWORK -HIGH IMPEDNE -INVERTER -NND NETWORK = = + PULL-DOWN PULL-UP PULL-DOWN PULL-UP R.M. Dansereau; v.. R.M. Dansereau; v.. HPTER II-5 WITH NETWORK ND NETWORK WITH NETWORK -INVERTER -NND NETWORK -NOR NETWORK HPTER II-6 WITH NETWORK OR NETWORK WITH NETWORK -NND NETWORK -NOR NETWORK -ND NETWORK NND INVERTER = NOR INVERTER = + R.M. Dansereau; v.. R.M. Dansereau; v..
4 HPTER II-7 WITH NETWORK XOR NETWORK WITH NETWORK -NOR NETWORK -ND NETWORK -OR NETWORK HPTER II-8 WITH NETWORK XNOR NETWORK WITH NETWORK -ND NETWORK -OR NETWORK -XOR NETWORK = + = + an this be implemented without the extra inverter at the output? nswer: Yes! R.M. Dansereau; v.. R.M. Dansereau; v.. HPTER II-2 WITH NETWORK FUNTION IMPLEMENTTION WITH NETWORK -XOR NETWORK -XNOR NETWORK -PULL-UP/PULL-DOWN HPTER II-2 WITH NETWORK EXMPLE PULL-UP WITH NETWORK -XNOR NETWORK -PULL-UP/PULL-DOWN -FUN. IMPLEMENTTION Most oolean functions can be easily implemented using switches. The basic rules are as follows Pull-up section of switch network Use complements for all literals in expression Use only pmo devices Form series network for an ND operation Form parallel network for an OR operation Pull-down section of switch network Use complements for all literals in expression Use only nmo devices Form parallel network for an ND operation Form series network for an OR operation To implement the oolean function given below, the following pull-up network could be designed. F = E( D + ( + ) ) D E F R.M. Dansereau; v.. R.M. Dansereau; v..
5 HPTER II-22 WITH NETWORK EXMPLE PULL-DOWN WITH NETWORK -PULL-UP/PULL-DOWN -FUN. IMPLEMENTTION -EXMPLE PULL-UP HPTER II-23 WITH NETWORK OMPLETED EXMPLE WITH NETWORK -FUN. IMPLEMENTTION -EXMPLE PULL-UP -EXMPLE PULL-DOWN To complete the switch design, the pull-down section for the oolean function must also be designed. Putting the pull-up and pull-down pieces together gives the following MO switch implementation of the oolean function. F = E( D + ( + ) ) D E F PULL-UP PULL-DOWN E D E F = E( D + ( + ) ) Notice how ND and OR become OR and ND circuits, respectively. D R.M. Dansereau; v.. R.M. Dansereau; v.. Fabrication Materials MO ubthreshold Region ubthreshold Region I ds, V gs V ubthreshold current is due to reverse bias leakage current of diode between diffusion and substrate EE 36 Lecture 2 3
6 MO Linear Region The inversion layer (channel) is symmetric, until: MO Linear Region Transverse electric field distorts the channel V 2 ds I ds = β ( V gs V t )V ds O V 2 ds V gs V t V 2 ds I ds = β ( V gs V t )V ds O V 2 ds V gs V t EE 36 Lecture 2 4 EE 36 Lecture 2 5 MO aturation Region hannel is pinched off when V gs V t V ds Photolithographic Process ilicon dioxide UV Radiation Photoresist (Negative ) ilicon hadow of mask feature ( a ) ( b ) Photo mask with opaque feature Hardened Photoresist ( c ) Photoresist stripped ( d ) ilicon dioxide etched where exposed urrent is swept through depletion region electric field after leaving channel. ( e ) EE 36 Lecture 2 6
7 Layout Example: MO Inverter Layout Example: MO Inverter et Pitch (place well and power/ground busses) dd Transistors (active, select, and poly) EE 36 Lecture 4 3 EE 36 Lecture 4 4 Layout Example: MO Inverter Layout Example: MO Inverter Make onnections (poly, metal, and cuts) dd ubstrate and Well ontacts EE 36 Lecture 4 5 EE 36 Lecture 4 6
![(contact cuts) [D] dd External Wiring and Resize EE 36](/docs-images/80/81583124/images/8-3.jpg "Lecture 4 7 EE 36 Lecture 3 3 Width/pacing Design")
8 Layout Example: MO Inverter Design Rules Minimum eparation [] Intralayer (all layers) Interlayer (active to poly/well/select) From Transistor Minimum Width (all layers) [] Minimum Overlap [] Past Transistor (poly, active) round ontact ut (all contacted layers) round ctive (well, select) Exact ize (contact cuts) [D] dd External Wiring and Resize EE 36 Lecture 4 7 EE 36 Lecture 3 3 Width/pacing Design Rules MO Inverter EE 36 Lecture 3 5
9 MO NND Gate MO NOR Gate Example: NND Gate (Vertical) Example: NND Gate (Horizontal) EE 36 Lecture 5 2 EE 36 Lecture 5 3
10 omplex Gates Euler Paths The gate function does not need to be primitive, or symmetric ny f ( x) may be implemented lgorithm:. put f ( x) in form with only ND, OR, and literals (use DeMorgans). 2. compute f using generalized DeMorgan s Theorem 3. construct complimentary networks using transistors in series for ND, and transistors in parallel for OR Note: There are many correct networks due to commutivity Out Mapping MO ircuits to Graphs ircuit Nodes Map to Graph Vertices Transistors Map to Graph Edges omplementary ircuit Networks Map to Dual Graphs V dd Gnd O t Out EE 36 Lecture 5 5 EE 36 Lecture 5 6 Euler Paths Describing an Euler Path Gnd V dd Out While an ordered list of edges only suffice to denote an Euler path, a complete description is an ordered list of nodes and edges For example: Path = {V dd,, I,, Out,, V dd } This form is useful for layout purposes Finding Euler Paths Out order =,, Find ll Euler Paths Find an n and a p Euler Path with Identical Labeling If No Identical Labeling, reak the Path Minimally EE 36 Lecture 5 7 EE 36 Lecture 5 8
11 Euler Path to Layout Map Euler Paths to MO Layout Place usses Place Transistors omplete Wiring tandard ell Layout In general, when laying out standard cells or other custom gate designs, there may not exist a Euler Path e.g., ( + D)E tandard cells for a particular process (e.g.,.35u HP MO) need not follow lamda spacing rules There are companies whose sole purpose is the creation and maintenance of standard cell libraries ustom layout is very time-intensive and laborious for large chips; therefore, custom layout is typically done only for critical paths Read hapters 3, 4 and 7 of Wolf EE 36 Lecture 5 9 EE 36 Lecture 5 omplex Gate vs Network of Gates omplex gate implementation of F ab c d omplex Gate vs Network of Gates Network of NND2/INV implementation
12 asic ells asic ells (cont) -bit M adder -bit register -bit logic unit 2x4 decoder it lice asic locks -bit adder + -bit logic unit 4 registers 4 registers + adder + logic unit = bit-slice will be stacked 6 times 4x6-bit registers, 6-bit adder, 6-bit logic unit
13 Matrix olver (2K) Matrix olver (2K) adence Encounter: placement ( sec), routing (2 sec) rea = 72x72um (45nm library), used 6 metal layers M M2 M3 M4 M5 M6 Matrix olver (2K) GDII shots: manufacturing-ready pecify all intra-cell details 32-bit Processor (2.7M) Placement took 739 sec, routing took 474 sec rea = xum, used metal layers
14 32-bit Processor (2.7M) 32-bit Processor (2.7M) M M2 M3 M7 M8 M9 M4 M5 M6 M Placement omparison Runtime: sec vs 739 sec Routing omparison Runtime: 2 sec vs 474 sec 2K 2.7M 2K 2.7M
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