EE141-Fall 2009 Digital Integrated Circuits
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1 EE141-Fall 2009 Digital Integrated Circuits Lecture 2 Integrated Circuit Basics: Manufacturing and Cost 1 1 Administrative Stuff Discussions start this Friday We have a third GSI Richie Przybyla, rjp@eecs OH: Wed. 4-5pm Lab: Tues. 12:30-3:30pm Labs start next week Homework #1 is due this Thursday Everyone should have an EECS instructional account Use cory, quasar, pulsar 2 2
2 Your EECS141 Week M OH (Milos) TBD Cory Lab (Milos) 353 Cory DISC* (Yue) 293 Cory T Lec (Elad) 277 Cory Lab (Richie) 353 Cory OH (Elad) 565 Cory W OH (Yue) TBD Cory OH (Richie) TBD Cory R F DISC* (Milos) 293 Cory Lec (Elad) 277 Cory Lab (Yue) 353 Cory * Discussion sections will cover identical material 3 OH (Elad) 565 Cory DISC* (TBA) 293 Cory Problem Sets Due 3 HSPICE Syntax Simple CMOS inverter.include '/home/ff/ee141/models/gpdk090_mos.sp TT_s1v * netlist Vdd vdd VIN in 0 PULSE ps 100ps 100ps 2ns 4ns M0 out in vdd vdd gpdk090_pmos1v L=100e-9 W=120e-9 M1 out in gnd gnd gpdk090_nmos1v L=100e-9 W=120e-9 R1 in gnd 10K R2 out vdd 100K * extra control information.options post=2 nomod * analysis.op.tran.01ns 3ns.DC VIN END 4 4
3 Last Lecture Last lecture Introduction, Moore s law, future of ICs Today s lecture Introduce basics of integrated circuit manufacturing and cost Reading: Ch 2.1, CMOS Manufacturing Process 6 6
4 The MOS Transistor Polysilicon Aluminum 7 7 The Manufacturing Process For a complete walk-through of the process (64 steps), check the Book web-page 8 8
5 Photo-Lithographic Process oxidation optical mask photoresist removal (ashing) photoresist coating stepper exposure process step Typical operations in a single photolithographic cycle (from [Fullman]). photoresist development spin, rinse, dry acid etch 9 9 Patterning of Si-substrate (a) Silicon base material Si-substrate (b) After oxidation and deposition of negative photoresist Si-substrate (c) Stepper exposure Photoresist UV-light Patterned optical mask Exposed resist Si-substrate Si-substrate Si-substrate Chemical or plasma etch Hardened resist (d) After development and etching of resist, chemical or plasma etch of (e) After etching Hardened resist (f) Final result after removal of resist 10 10
6 Advanced Metallization A Modern CMOS Process gate-oxide TiSi 2 AlCu Tungsten n+ p-well p-epi poly n-well p+ p+ Dual-Well Shallow-Trench Trench-Isolated CMOS Process 12 12
7 Transistor Layout Cross-Sectional View poly p-well n+ poly Layout View p-well Cost 14 14
8 Cost of Integrated Circuits NRE (non-recurrent engineering) costs - fixed Independent of volume (i.e., number of units made/sold) Examples: design time and effort, mask generation, equipment, etc. Recurrent costs - variable proportional to volume Examples: silicon processing, packaging, test Most of these proportional to chip area NRE Cost is Increasing 16 16
9 Total Cost Cost per IC cost per IC = variable cost per IC + fixed cost volume Variable cost cost of die + variable cost = cost of die test + cost of final test yield packaging Die Cost Wafer Single die cost of die = cost of wafer dies per wafer * die yield From:
10 Wafer size AMD Athlon 8 (200mm) 12 (300mm) 12 (300mm) 90nm CMOS 90nm CMOS 65nm CMOS From: Yield π Dies per wafer = No. of good chips per wafer Y = 100% Total number of chips per wafer Wafer cost Die cost = Dies per wafer Die yield ( wafer diameter/2) die area 2 π wafer diameter 2 die area 20 20
11 Defects Yield = 1/4 Yield = 19/24 α defects per unit area die area die yield = 1 +, α where α is approximately 3 die cost -1-3 ( die/wafer die area )( yield die area ) die area 4 Cost per Transistor cost: -per-transistor Fabrication cost per transistor
12 Next Lecture CMOS transistors as switches How to build an inverter Design metrics 23 23
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