3D SOI elements for System-on-Chip applications

Transcription

1 Advanced Materials Research Online: ISSN: , Vol. 276, pp doi: / Trans Tech Publications, Switzerland 3D SOI elements for System-on-Chip applications І.T. Kogut 1, A.A. Druzhinin 2, V.I. Holota 1 1 Precarpathian National University, Ivano-Frankivsk, Ukraine 2 National University Lvivska Politechnika, Lviv, Ukraine Keywords: technology, SOI-structure, integrated microsystem Abstract. Base technology of local 3D SOI-structures formation has been proposed. Using this technology the electrical characteristics were developed and simulated of following original device elements for the microsystem applications: standard and matrix SOI CMOS-transistors with 3D gates, switching elements on Schottky diodes, contact electrodes with 3D surface, elements for highly sensitive integral accelerometers with registration of a field emission current, hermetical microcavities and microchannels under the surface of a SOI-substrate, field emission silicon microcathodes. Introduction In last years a new direction in creation of the integrated microsystems-on-chip (MSoC) is intensively developed. In MSoC manufacturing traditional, planar CMOS, bipolar and Bi-CMOS technologies are used which allow one to create elements for both digital and analog blocks, sensor and actuator elements. However, from the point of view of increase of element integration and speed, stability external influencing factors, and also for creation of device structures with 3D architecture, SOI structures have greater opportunities. Therefore complex researches on creation of new technologies of SOI structures formation and creations on such structures of new device elements for integrated MSoC and their modeling is an actual problem. The basic technology for local 3D SOI structures Traditionally for creation of elements of the integrated MSoC with SOI structure SOI wafers are used which are produced on SIMOX, ELTRAN, SmartCut and Unibond technologies [1]. The SOI film has identical thickness on all surfaces of such wafers. However from the point of view of design of MSoC elements essentially the best advantages can be achieved with the use of SOI layers of different thicknesses which can be formed in the necessary places on a wafer. It allows one to use for the element base both planar and 3D SOI structures, and bulk silicon. The authors [2, 3] develop technology of formation of local 3D SOI structures. For practical realization of this technology the double projective photolithography, plasma-chemical etching, local oxidation and surface planarization are used. Local three-dimensional structures are formed by stripes of 1-2 micrometer width and of the desired length. Thus, highly technological and reliable isolation both between local stripes and between devices structures is actually possible. Such an approach allows one to reduce essentially design rules and to increase a degree of integration of elements on crystal, and also creates conditions and a constructional material for high-voltage elements of the IC and MSoC. Thus, a starting material in the obtained structure is a superficial layer on a silicon wafer, which due to nondestructive technology (unlike high-energy impurity-dopant incorporation, for example in SIMOX technology) provides high crystal perfection and parameters of silicon. On local 3D SOI structures it is possible to form both contact electrodes, and transistor structures. The device transistor 3D SOI MOS-structure is shown in Fig.1 (in figures are designated: 1 - bulk silicon wafer, 2 - local thermal oxide, 3 gate of 3D SOI MOS-transistor, 4 gate insulator, 5 3D SOI-element). All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-10/05/16,09:58:48)

2 138 Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices On local 3D SOI structures it is possible to form contact electrodes to structures of the different shape. For different contact electrodes we have investigated by modeling the effects of voltage, carrier density in the channel area on distribution of potentials and dielectric field intensity, see Fig. 2 [3]. By modeling we have also investigated the influence of a gate potential, a gate surface contour and carrier density in the channel area for 3D SOI MOS-transistors on distribution of potentials, dielectric field intensity, see Fig. 3 [4]. Fig. 1. 3D SOI MOS-structure. It is found, that such distributions are identical for identical forms of surfaces in the diode and MOS-transistor structures. For structures with the - shaped gate a current density and thickness of the inversion channel are non-uniform (Fig. 3, a). The highest density is on angular segments, lower one is on vertical walls and the lowest one is on a horizontal surface of the channel area. With greater radii of rounding of an angular segment the current density decreases. In a construction of the 3D SOI MOS-transistor with a cylindrical surface contour of gate, the thickness of the inversion conduction channel and carrier density in the channel are mostly uniform (Fig. 3, b). Such 3D SOI MOS-transistors, in comparison with known ones, have the best switching and noise performances due to the uniform distribution of a threshold voltage on a channel width. Transistors in Fig. 3, a, b are insulated from the wafer by the dielectric, and those in Fig. 3, c, d have an electric contact with the wafer through the channel between two bulk insulating areas. If bulk areas are filled not with insulator, but with a material with charge carriers, then by connecting it to the proper potential it is possible to control both a charge under the gate, and a floating charge. By modeling it is found, that the type of the bulk charge and of material in microcavities modulate channels both under the gate of the transistor, and in the places where the channel area is connected to the substrate. These results open opportunities for construction of new designs of sensitive elements of microsystems or microlaboratories on a crystal. Such microsystems can determine concentration or presence of some material in microvolumes. Using the proposed local three-dimensional SOI-structures, the electrical characteristics have been developed and simulated for following original device elements for the microsystem applications: standard and matrix SOI CMOS-transistors with 3D gates, switching elements on Sсhottky diodes, contact electrodes with 3D surface contour, elements for highly sensitive integral accelerometers with registration of variations of a field emission current, hermetical microcavities and microchannels under the surface of the SOI-substrate, field emission silicon microcathodes with control circuits. The proposed type of microcavities and channels can be used also for elements of resonators, the optical paths, filled by metal - as powerful conductors, and filled by liquid or electrolyte - as microradiators or micropower sources. Switching elements on Schottky diodes In Fig. 4 the cross-sections of the developed switching elements on Schottky diodes, with the use of two types of local SOI-structures, namely, suggested 3D SOI-structure (Fig. 4, a) and planar structure (Fig. 4, b) are shown [5]. Control electrode (gate) forms Schottky diodes on lateral layers of mono-si (area 2 - area 3, Fig. 4) with donor density 1x10 15 cm -3. Source and drain forms ohmic contacts on lateral layers of mono-si (area 2 - area 4, area 2 - area 5, Fig. 4) with donor density 1x10 19 cm -3. The current-voltage characteristics of switching elements are shown in Fig. 5. The speed of such switching element was estimated to be GHz.

3 Advanced Materials Research Vol c) d) Fig. 2. Distribution of potentials and intensity of an electric field in 3D SOI structures for contacts of the different form: a) planar; b) -shaped; c) -shaped; d) -shaped; 1 bulk Si; 2 SOI Si; 3 SiO 2 ; 4 contact. c) d) Fig. 3. Distribution of potentials and intensity of an electric field in 3D SOI MOS-structures for gates of the different form: a) -shaped; b) cylindrical; c) -shaped; d) -shaped; 1 bulk Si; 2 SOI Si; 3 SiO 2 ; 4 gate. Fig. 4. Switching element on Schottky diodes: 1 SiO 2 layer in local SOI structure; 2 Si layer in local SOI structure; 3 gate; 4 source; 5 drain; 6 isolating trench; 7 substrate.

4 140 Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices c) Fig. 5. Current-voltage characteristics of Schottky diodes: a) Vg<0; b) Vg=0; c) Vg>0. Contact electrode with 3D surface contour The 3D metal or polysilicon contact electrode to an element of integrated device structure is proposed. This contact electrode in comparison with the standard one has the area smaller by %. In Fig. 6, a-d, the cross-section and current-voltage characteristics of standard and proposed 3D contact electrode are shown. The results of simulation and measurements show that the conductivity of 3D contacts is 1.5 times higher as compared to the standard ones with the identical areas on the crystal surface. c) d) Fig. 6. Cross-section section of contacts and current-voltage characteristics: a), b) standard contact; c), d) 3D contact; 1 physical contact (anode); 2 layer of metal (Al), 3 layer of SiO 2 ; 4 layer of poly-si; 5 Si substrate; 6 physical contact (cathode); 7 layer of SiO 2 insulator. In Fig. 7 the schematic topology of the proposed contact electrodes between layers of metal (1) and polysilicon gate (5), between layers of polysilicon gate (5) and the silicon bus of SOI MOStransistor source (4) is shown.

5 Advanced Materials Research Vol Fig. 7. Schematic topology of the SOI MOS transistor with different types of contacts to electrodes: 1 metal bus (Al-Si alloy); 2 contact window in the gate insulator; 3, 6, 8 contact windows in the interlayer insulator; 4 source and drain areas; 5 poly-si gate; 7 SiO 2 surface in SOI structure. Еlements for highly sensitive integral accelerometer Using the basic technology of local 3D SOI structures, it is possible to create the movable and unmovable field emission microcathodes for constructing, for example, the highly sensitive accelerometer, which record changes in the emission current. c) Fig. 8. Highly sensitive integral accelerometer: a) cross-section in xy plain; b) cross-section in xz plain; c) cross-section in yz plain; 1 movable element, 2 cavity filled by SiO 2, 3 fixed element (substrate), 4 cavity, 5 the lines of electric field. Hermetical microcavities Fig. 9. Cross-section of a hermetical microcavity: 1 substrate (100); 2 thick local thermal oxide; 3 thin oxide; 4 silicon nitride; 5 polysilicon; 6 hermetical cavity.

6 142 Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices Using the basic technology of formation local 3D SOI structures it is possible to create also hermetic microcavities under the surface of bulk silicon [7]. To isolate cavities two techniques can be used. The first technique is the deposition of polysilicon on the adjascent parts of Si 3 N 4 (Fig. 9, a). In the second technique microcavities are isolated by SiO 2 (Fig. 9, b). Pressure sensor on SOI structure Using local planar structures [8] authors develop a sensor for pressures in the range MPa. Fig. 10. Pressure sensor. Field emission microcathode on local 3D SOI structures Since the local structures may have different thicknesses, they can be used to form sufficiently large volume devices. The technology was designed and simulated for manufacturing of one- and two-electrode silicon microcathodes on such local structures. The proposed technology allows creating both tip and edge microcathodes (Fig. 10). Such microcathodes can focus electron beams in the anode plane in the images of different shapes and sizes. c) Fig. 10. Field emissiom microcathode on SOI-structure: a) one tip; b) multi tips; c) with edges; 1 Si layer, 2 protective coating layer of W; 3 SiO 2 layer ; 4 extraction electrode. Focusing ability of electron optics of the microcathode with two electrodes are shown in Fig. 11. Results of computer modelling show, that such microcathode can focus electron beams in anode area to diameter up to 0.8 µm.

7 Advanced Materials Research Vol Fig. 11. Microcathode with two electrodes: a) cross-section; b) electron optics; 1 Si layer, 2 the protective layer of W; 3 SiO 2 layer; 4 extraction microcathode; 5 focusing electrode; 6 the equipotential lines; 7 electron trajectories; 8 anode plane. To stabilize the field emission current of a silicon microcathode it can be used in series connection with high-voltage transistor with breakdown voltage of 150 V (Fig.12). For such connection the microcathode is fabricated in the drain area of the high-voltage transistor. Microcathode dimensions and the breakdown voltage of the high-voltage transistor selected from the conditions for field-emission currents of 10 µa. Linear regulation of a field-emission current of the microcathode in the interval 10 na 10 µa is carried out by the pulse-amplitude modulator on SOI MOS transistors with different values of width and lengths of channels (W/R). The necessary combination of transistors of a pulse-amplitude regulator is set by programming of SRAM memory cells. Programming of SRAM memory cells are carried out through I/O data buffers. The layout of microcathode integrated with control circuit are shown in Fig. 13. Fig. 12. Microcathode integrated with high voltage transistor on local 3D SOI-structure: 1 source contact; 2 gate; 3 extraction and focusing electrode; 4 source; 5 undergate area; 6 pyrolytic SiO 2 ; 7 high-resistance area; 8 drain; 9 SiO 2.

8 144 Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices Fig. 13. The layout of microcathode integrated with control circuit: 1 pulse-amplitude modulator; 2 voltage dividers; 3 static type memory cells; 4 I/O data buffers for memory cells; 5 microcathode. Conclusion The technology of local 3D SOI structures formation is proposed. On such structures it is possible to create the integrated elements, both on a surface, that is planar devices, and other devices with 3D configurations. Examples of device 3D SOI-structures are shown MOS transistors, switching elements on Schottky diodes, contact electrode, elements for highly sensitive integral accelerometer, hermetical microcavities, pressure sensor, emission microcathode. They can be used as elements of MSoC. Thus, the developed instrument elements on 3D SOI structures can be used in design of integrated SOI devices with three-dimensional architecture. References [1] Colinge J.P. Silicon-on-Insulator Technology: Materials to VLSI, 2nd Edition / Jean-Pierre Colinge. NY: Kluwer Academic Publishers p. [2] Patent for the useful model UA. Method of preparing the local three-dimensional structures the silicon-on-insulator. I.T. Kohut, V.I. Holota, A.O. Drushynin, S.V. Sapon Published , Bulletin p. [3] I.T. Kohut: Physics and chemistry of solid state Vol. 1 (2008), p [4] I.T. Kohut et al.: bulletin of National University Lvivska Polytechnika Vol. 646 (2009), p.86. [5] Patent for the useful model UA. Switching element on Schottky diodes with the structures silicon on the insulator. Kohut I.T., Holota V.I., Drushynin A.O. Published , Bulletin p. [6] Patent for the useful model UA. Contact in the integral devices with the structures silicon on the insulator. Kohut I.T., Drushynin A.O., Holota V.I. Published , Bulletin p. [7] Patent for useful model UA. Method of hermetic cavities formation in silicon wafer. I.T. Kohut, V.I. Holota Published , Bulletin c. [8] Patent for useful model UA. Method of local microstructures formation of type "silicon-on-insulator". Kohut I.T., Holota V.I., Dryshynin A.O., Sapon S.V. Published Bulletin c. [9] A. Druzhynin, V. Holota, I. Kohut, S. Sapon and Y. Khoverko: Electrochem. Soc. Trans., Vol 14 (2008), p. 569

9 Nanoscaled Semiconductor-on-Insulator Materials, Sensors and Devices / 3D SOI Elements for System-on-Chip Applications /