EE C245 ME C218 Introduction to MEMS Design
|
|
|
- Virginia King
- 6 years ago
- Views:
Transcription
1 EE C45 ME C18 Introduction to MEMS Design Fall 008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 9470 Lecture 7: Noise & Integration ti EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 1
2 Lecture Outline Reading: Senturia, Chpt. 16 Lecture Topics: Noise MEMS/Transistor Integration Wrap Up Final Exam Next Week EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08
3 Noise EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 3
4 Noise Noise: Random fluctuation of a given parameter I(t) In addition, a noise waveform has a zero average value Avg. value (e.g. could be DC current) I D I(t) t We can t handle noise at instantaneous times But we can handle some of the averaged effects of random fluctuations by giving noise a power spectral density representation Thus, represent noise by its mean-square value: Let i ( t ) = I ( t ) I D Then i 1 = ( I I ) = D lim I T T T 0 I D dt EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 4
5 Noise Spectral Density We can plot the spectral density of this mean-square value: i Δf [units /Hz] One-sided spectral density used in circuits measured by spectrum analyzers Two-sided spectral density (1/ the one-sided) d) Often used in systems courses i = integrated mean-square noise spectral density over all frequencies (area under the curve) EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 5
6 Inputs Circuit Noise Calculations Deterministic Outputs v i ( jω) ) ( jω) ) H ( jω) S i (ω ) S o o( (ω ) Deterministic: Random: Linear Time-Invariant System Random v π v o (t) ( jω) ω o v o t ω ( jω) H ( jω) v ( jω) o = i v o ω ο S o (t) S ( jω) ) t S o ω ο Mean square spectral density * Random: S ( ω ) = [ H ( j ω ) H ( j ω )] S ( ω ) = H ( j ω ) S ( ω ) o i S ( ω) = H ( jω) S ( ω) How is it we o Root mean square amplitudes i can do this? EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 6 i ω
7 Handling Noise Deterministically Can do this for noise in a tiny bandwidth (e.g., 1 Hz) S n v n n 1 = S1 ( f Δf ω ο B ( jω) ) ω Can approximate this v = S ( f ) B v n 1 S S o i 1 ( ω ο ω ω o ω [This is actually the principle by which oscillators work oscillators are just noise going through a tiny bandwidth filter] B by a sinusoidal voltage generator (especially for small B, say 1 Hz) v o τ ~ (t) 1 B A cosω t Why? Neither the amplitude nor the phase of a signal can change appreciably within a time period 1/B. EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 7 o t
8 Systematic Noise Calculation Procedure H ( jω) H5( jω) General Circuit With Wth Several Noise Sources v n i n1 v n3 i n5 i n4 v n6 v on H1( jω) Assume noise sources are uncorrelated 1. For i n1, replace w/ a deterministic source of value in1 n 1 = i Δff (1Hz) EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 8
9 Systematic Noise Calculation Procedure v 1( ω) i 1( ω) H ( jω). Calculate n (treating it like a deterministic signal) 3. Determine on = v on1 = in1 H ( jω) 4. Repeat for each noise source:,, i n1 1 v n n3. p f,,v n3 5. Add noise power (mean square values) v ontot = v on1 + v on + v on3 + v on4 +L v ontot = v on1 + von + von3 + von4 +L Total rms value EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 9
10 Minimum Detectable Signal (MDS) Minimum Detectable Signal (MDS): Input signal level when the signal-to-noise ratio (SNR) is equal to unity Sensed Signal Sensor Scale Factor Circuit Gain Output t Sensor Noise Sensor Circuit Output Noise Signal Conditioning Circuit Includes desired output plus noise The sensor scale factor is governed by the sensor type The effect of noise is best determined via analysis of the equivalent circuit for the system EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 10
11 LF356 Op Amp Data Sheet EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 11
12 Minimum Detectable Signal (MDS) Minimum Detectable Signal (MDS): Input signal level when the signal-to-noise ratio (SNR) is equal to unity Sensed Signal Sensor Scale Factor Circuit Gain Output t Sensor Noise Sensor Circuit Output Noise Signal Conditioning Circuit Includes desired output plus noise The sensor scale factor is governed by the sensor type The effect of noise is best determined via analysis of the equivalent circuit for the system EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 1
13 Move Noise Sources to a Common Point Move noise sources so that all sum at the input to the amplifier circuit (i.e., at the output of the sense element) Then, can compare the output of the sensed signal directly to the noise at this node to get the MDS Sensed Signal Sensor Scale Factor Circuit Gain Output Sensor Noise Sensor Circuit Input- Referred Noise Signal Conditioning Circuit Includes desired output plus noise EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 13
14 r F c Gyro Readout Equivalent Circuit (for a single tine) Noise Sources r r r = mac = m ( x & d Ω ) i f F c l x c x f r x r x η e :1 i o v x i 0 ia C p ia - + R f v Gyro Sense Element Signal Conditioning Circuit Output Circuit (Transresistance Amplifier) Easiest to analyze if all noise sources are summed at a common node EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 14
15 r F c Gyro Readout Equivalent Circuit (for a single tine) r r r = mac = m ( x & d Ω ) Noise Sources Noiseless l x c x f r r x r x η e :1 i o v F x i 0 c eq C p eq - + R f v Gyro Sense Element Output Circuit Signal Conditioning Circuit (Transresistance Amplifier) v eq i eq Here, and are equivalent input-referred voltage and current noise sources EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 15
16 r F c = Example: Gyro MDS Calculation (cont) r ma c = l x c x r r m ( x & Ω) f r x r x d η e :1 i o v F x& i v 0 c s eq C p eq - + R f Noiseless Now, find the i eqtot entering the amplifier input: EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 16
17 Example: Gyro MDS Calculation (cont) EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 17
18 r F c = Example: Gyro MDS Calculation (cont) r ma c = l x c x r r m ( x & Ω) f r x r x d η e :1 i o v F x& i v 0 c s eq C p eq - + R f Noiseless First, find the rotation to i o transfer function: EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 18
19 Example: Gyro MDS Calculation (cont) EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 19
20 Sensing Circuits (cont) EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 0
21 Problems With Pure-C Position Sensing To sense position (i.e., displacement), use a capacitive load EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 1
22 F d1 Ele ectrode The Op Amp Integrator Advantage x d 1 d b k e C 1io - m lectrod E The virtual ground provided by the ideal op amp eliminates the parasitic capacitance C p R 1 R >> sc (for biasing) C p 0 + v i C C 1 1 v 1 V P EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08
23 Integration of MEMS and Transistors EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 3
24 Merged MEMS/Transistor Technologies (Process Philosophy) MEMS-Last: MEMS-First: Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEMS-first or MEMS-last: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 4
25 Analog Devices BiMEMS Process Interleaved MEMS and 4 μm BiMOS processes (8 masks) Diffused n+ runners used to interconnect MEMS & CMOS Relatively deep junctions allow for MEMS poly stress anneal Used to manufacture the ADXL-50 accelerometer and Analog Devices family of accelerometers EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 5
26 Analog Devices BiMEMS Process (cont) Examples: Old New Analog Devices ADXL 78 Analog Devices ADXL-0 Multi-Axis Accelerometer Can you list the advances in the process from old to new? EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 6
27 50 nm CMOS Cross-Section D D G Sub S nd Level Metal Interconnect (e.g., Cu) G Sub S S G D S G D 1 st Level Metal Interconnect (e.g., Al) LPCVD SiO Polysilicon Gate CVD Tungsten LOCOS Oxidation TiSi Contact Barrier TiN Local P + N P+ N + P N + Interconnect N Well - PMOS Substrate P Well - NMOS Substrate Silicon Substrate P Lightly Doped Drain (LDD) 8 masks and a lot more complicated than MEMS! EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 7
28 Merged MEMS/Transistor Technologies (Process Philosophy) Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEMS-first or MEMS-last: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 8
29 MEMS-First Integration Problem: μstructural topography interferes with lithography difficult to apply photoresist for submicron circuits Soln.: build μmechanics in a trench, then planarize before circuit processing [Smith et al, IEDM 95] EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 9
30 MEMS-First Ex: Sandia s imems Used to demonstrate functional fully integrated oscillators Issues: lithography h and etching may be difficult in trench may limit dimensions (not good for RF MEMS) μmechanical material must stand up to IC temperatures (>1000 o C) problem for some metal materials might be contamination issues for foundry IC s [Smith et al, IEDM 95] EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 30
![05] μmechanical Device EE C45:](/docs-images/79/79150430/images/31-6.jpg "Introduction to MEMS Design")
31 Bosch/Stanford MEMS-First Process Single-crystal silicon microstructures sealed under epi-poly encapsulation covers Many masking steps needed, but very stable structures Resonator Epi-Poly Seal Epi-Poly Cap Contact Substrate Epi-silicon for CMOS Transistor Circuits Vacuum Chamber [Kim, Kenny Trans 05] μmechanical Device EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 31
32 Merged MEMS/Transistor Technologies (Process Philosophy) Mixed: problem: multiple passivation/protection steps large number of masks required problem: custom process for each product MEMS-first or MEMS-last: adv.: modularity flexibility less development time adv.: low pass./protection complexity fewer masks EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 3
33 Berkeley Polysilicon MICS Process Uses surface-micromachinedpolysilicon microstructures with silicon nitride layer between transistors & MEMS Polysilicon dep. T~600 o C; nitride dep. T~835 o C 1100 o C RTA stress anneal for 1 min. metal and junctions must withstand temperatures ~835 o C tungsten metallization used with TiSi contact barriers in situ doped structural polysi; rapid thermal annealing EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 33
34 Single-Chip Ckt/MEMS Integration Completely monolithic, low phase noise, high-q oscillator (effectively, an integrated crystal oscillator) Oscilloscope Output Waveform [Nguyen, Howe 1993] To allow the use of >600 o C processing temperatures, tungsten (instead of aluminum) is used for metallization EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 34
35 Usable MEMS-Last Integration Problem: tungsten is not an accepted primary interconnect metal Challenge: retain conventional metallization minimize post-cmos processing temperatures explore alternative structural materials (e.g., plated nickel, SiGe [Franke, Howe et al, MEMS 99]) Limited set of usable structural materials not the best situation, but workable EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 35
36 UCB Poly-SiGe MICS Process μm standard CMOS process w/ Al metallization P-type poly-si 0.35 Ge 0.65 structural material; poly-ge sacrificial material Process: Passivate CMOS w/ 400 o C Open vias to interconnect runners Deposit & pattern ground plane RTA anneal to lower resistivity (550 o C, 30s) Transistor Circuits EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 36
37 Wrap Up EE C45: Introduction to MEMS Design Lecture 7 C. Nguyen 1/8/08 37
EE C247B ME C218 Introduction to MEMS Design Spring 2016
EE C247B ME C218 Introduction to MEMS Design Spring 2016 Prof. Clark T.C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Module 16: Sensing
Surface Micromachining
Surface Micromachining An IC-Compatible Sensor Technology Bernhard E. Boser Berkeley Sensor & Actuator Center Dept. of Electrical Engineering and Computer Sciences University of California, Berkeley Sensor
EE C245 ME C218 Introduction to MEMS Design Fall 2010
Instructor: Prof. Clark T.-C. Nguyen EE C245 ME C218 Introduction to MEMS Design Fall 2010 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley
EE C245 ME C218 Introduction to MEMS Design Fall 2007
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 1: Definition
EE C245 ME C218 Introduction to MEMS Design
EE C245 ME C218 Introduction to MEMS Design Fall 2008 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 1: Definition
2.8 - CMOS TECHNOLOGY
CMOS Technology (6/7/00) Page 1 2.8 - CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical
CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs
CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1
Lecture 020 ECE4430 Review II (1/5/04) Page 020-1 LECTURE 020 ECE 4430 REVIEW II (READING: GHLM - Chap. 2) Objective The objective of this presentation is: 1.) Identify the prerequisite material as taught
Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics
Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor
420 Intro to VLSI Design
Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem
Topic 3. CMOS Fabrication Process
Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter
Chapter 3 Basics Semiconductor Devices and Processing
Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and
EE C245 / ME C218 INTRODUCTION TO MEMS DESIGN FALL 2011 PROBLEM SET #2. Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory.
Issued: Tuesday, Sept. 13, 2011 PROBLEM SET #2 Due (at 7 p.m.): Tuesday, Sept. 27, 2011, in the EE C245 HW box in 240 Cory. 1. Below in Figure 1.1 is a description of a DRIE silicon etch using the Marvell
EE C245 ME C218 Introduction to MEMS Design
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 21: Gyros
FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag
FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to
CMP for More Than Moore
2009 Levitronix Conference on CMP Gerfried Zwicker Fraunhofer Institute for Silicon Technology ISIT Itzehoe, Germany gerfried.zwicker@isit.fraunhofer.de Contents Moore s Law and More Than Moore Comparison:
Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.
Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk
EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng
EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html
Lecture 10: Accelerometers (Part I)
Lecture 0: Accelerometers (Part I) ADXL 50 (Formerly the original ADXL 50) ENE 5400, Spring 2004 Outline Performance analysis Capacitive sensing Circuit architectures Circuit techniques for non-ideality
EE C245 ME C218 Introduction to MEMS Design
EE C245 ME C218 Introduction to MEMS Design Fall 2007 Prof. Clark T.-C. Nguyen Dept. of Electrical Engineering & Computer Sciences University of California at Berkeley Berkeley, CA 94720 Lecture 20: Equivalent
Lecture 0: Introduction
Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power
Chapter 15 Summary and Future Trends
Chapter 15 Summary and Future Trends Hong Xiao, Ph. D. hxiao89@hotmail.com www2.austin.cc.tx.us/hongxiao/book.htm Hong Xiao, Ph. D. www2.austin.cc.tx.us/hongxiao/book.htm 1 The 1960s First IC product Bipolar
ECE4902 B2015 HW Set 1
ECE4902 B2015 HW Set 1 Due in class Tuesday November 3. To make life easier on the graders: Be sure your NAME and ECE MAILBOX NUMBER are prominently displayed on the upper right of what you hand in. When
EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02
EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic
RF MEMS for Low-Power Communications
RF MEMS for Low-Power Communications Clark T.-C. Nguyen Center for Wireless Integrated Microsystems Dept. of Electrical Engineering and Computer Science University of Michigan Ann Arbor, Michigan 48109-2122
Micromechanical Circuits for Wireless Communications
Micromechanical Circuits for Wireless Communications Clark T.-C. Nguyen Center for Integrated Microsystems Dept. of Electrical Engineering and Computer Science University of Michigan Ann Arbor, Michigan
+1 (479)
Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable
Final Exam Topics. IC Technology Advancement. Microelectronics Technology in the 21 st Century. Intel s 90 nm CMOS Technology. 14 nm CMOS Transistors
ANNOUNCEMENTS Final Exam: When: Wednesday 12/10 12:30-3:30PM Where: 10 Evans (last names beginning A-R) 60 Evans (last names beginning S-Z) Comprehensive coverage of course material Closed book; 3 sheets
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras
VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 40 BICMOS technology So, today we are going to have the last class on this VLSI
2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)
1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic
Vibrating RF MEMS for Low Power Wireless Communications
Vibrating RF MEMS for Low Power Wireless Communications Clark T.-C. Nguyen Center for Wireless Integrated Microsystems Dept. of Electrical Engineering and Computer Science University of Michigan Ann Arbor,
PROBLEM SET #7. EEC247B / ME C218 INTRODUCTION TO MEMS DESIGN SPRING 2015 C. Nguyen. Issued: Monday, April 27, 2015
Issued: Monday, April 27, 2015 PROBLEM SET #7 Due (at 9 a.m.): Friday, May 8, 2015, in the EE C247B HW box near 125 Cory. Gyroscopes are inertial sensors that measure rotation rate, which is an extremely
Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.
Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-
EE 410: Integrated Circuit Fabrication Laboratory
EE 410: Integrated Circuit Fabrication Laboratory 1 EE 410: Integrated Circuit Fabrication Laboratory Web Site: Instructor: http://www.stanford.edu/class/ee410 https://ccnet.stanford.edu/ee410/ (on CCNET)
Experiment 3 - IC Resistors
Experiment 3 - IC Resistors.T. Yeung, Y. Shin,.Y. Leung and R.T. Howe UC Berkeley EE 105 1.0 Objective This lab introduces the Micro Linear Lab Chips, with measurements of IC resistors and a distributed
Advanced Digital Integrated Circuits. Lecture 2: Scaling Trends. Announcements. No office hour next Monday. Extra office hour Tuesday 2-3pm
EE241 - Spring 20 Advanced Digital Integrated Circuits Lecture 2: Scaling Trends and Features of Modern Technologies Announcements No office hour next Monday Extra office hour Tuesday 2-3pm 2 1 Outline
INFN Laboratori Nazionali di Legnaro, Marzo 2007 FRONT-END ELECTRONICS PART 2
INFN Laboratori Nazionali di Legnaro, 6-30 Marzo 007 FRONT-END ELECTRONICS PART Francis ANGHINOLFI Wednesday 8 March 007 Francis.Anghinolfi@cern.ch v1 1 FRONT-END Electronics Part A little bit about signal
Basic Fabrication Steps
Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor
EE 230 Lab Lab 9. Prior to Lab
MOS transistor characteristics This week we look at some MOS transistor characteristics and circuits. Most of the measurements will be done with our usual lab equipment, but we will also use the parameter
EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1
EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules
Semiconductor Physics and Devices
Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because
IWORID J. Schmitz page 1. Wafer-level CMOS post-processing Jurriaan Schmitz
IWORID J. Schmitz page 1 Wafer-level CMOS post-processing Jurriaan Schmitz IWORID J. Schmitz page 2 Outline Introduction on wafer-level post-proc. CMOS: a smart, but fragile substrate Post-processing steps
Alternatives to standard MOSFETs. What problems are we really trying to solve?
Alternatives to standard MOSFETs A number of alternative FET schemes have been proposed, with an eye toward scaling up to the 10 nm node. Modifications to the standard MOSFET include: Silicon-in-insulator
IFSIN. WEB PAGE Fall ://weble.upc.es/ifsin/
IFSIN IMPLEMENTACIÓ FÍSICA DE SISTEMES INTEGRATS NANOMÈTRICS IMPLEMENTACIÓN N FÍSICA F DE SISTEMAS INTEGRADOS NANOMÉTRICOS PHYSICAL IMPLEMENTATION OF NANOMETER INTEGRATED SYSTEMS Fall 2008 Prof. Xavier
University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences. EECS 40 Midterm II
University of California at Berkeley College of Engineering Dept. of Electrical Engineering and Computer Sciences EECS 40 Midterm II Fall 1998 Prof. Roger T. Howe November 19, 1998 Name: Student ID: Guidelines
Design cycle for MEMS
Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor
Device Technologies. Yau - 1
Device Technologies Yau - 1 Objectives After studying the material in this chapter, you will be able to: 1. Identify differences between analog and digital devices and passive and active components. Explain
ECEN474/704: (Analog) VLSI Circuit Design Fall 2016
ECEN474/704: (Analog) VLSI Circuit Design Fall 2016 Lecture 1: Introduction Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements Turn in your 0.18um NDA form by Thursday Sep 1 No
Micromechanical Signal Processors for Low-Power Communications Instructor: Clark T.-C. Nguyen
First International Conference and School on Nanoscale/Molecular Mechanics: Maui, HI; May 2002 School Lecture/Tutorial on Micromechanical Signal Processors for Low-Power Communications Instructor: Clark
Semiconductor Detector Systems
Semiconductor Detector Systems Helmuth Spieler Physics Division, Lawrence Berkeley National Laboratory OXFORD UNIVERSITY PRESS ix CONTENTS 1 Detector systems overview 1 1.1 Sensor 2 1.2 Preamplifier 3
Semiconductor Memory: DRAM and SRAM. Department of Electrical and Computer Engineering, National University of Singapore
Semiconductor Memory: DRAM and SRAM Outline Introduction Random Access Memory (RAM) DRAM SRAM Non-volatile memory UV EPROM EEPROM Flash memory SONOS memory QD memory Introduction Slow memories Magnetic
Physics 160 Lecture 11. R. Johnson May 4, 2015
Physics 160 Lecture 11 R. Johnson May 4, 2015 Two Solutions to the Miller Effect Putting a matching resistor on the collector of Q 1 would be a big mistake, as it would give no benefit and would produce
(a) (d) (e) (b) (c) (f) 3D-NAND Flash and Its Manufacturing Process
3D-NAND Flash and Its Manufacturing Process 79 (d) Si Si (b) (c) (e) Si (f) +1-2 (g) (h) Figure 2.33 Top-down view in cap oxide and (b) in nitride_n-2; (c) cross-section near the top of the channel; top-down
Semiconductor Devices
Semiconductor Devices - 2014 Lecture Course Part of SS Module PY4P03 Dr. P. Stamenov School of Physics and CRANN, Trinity College, Dublin 2, Ireland Hilary Term, TCD 3 th of Feb 14 MOSFET Unmodified Channel
Micromachining Technologies for Miniaturized Communication Devices
Micromachining Technologies for Miniaturized Communication Devices Clark T.-C. Nguyen Center for Integrated Sensors and Circuits Department of Electrical Engineering and Computer Science University of
EECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,
Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007
6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 33-1 Lecture 33 - The Short Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 30, 2007 Contents: 1. MOSFET scaling
Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI
1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward
Signal Integrity Design of TSV-Based 3D IC
Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST joungho@ee.kaist.ac.kr http://tera.kaist.ac.kr 1 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues
EE C245 - ME C218 Introduction to MEMS Design Fall Today s Lecture
EE 45 ME 8 Introduction to MEMS Design Fall 003 Roger Howe and Thara Srinivasan Lecture 6 Micromechanical Resonators I Today s Lecture ircuit models for micromechanical resonators Microresonator oscillators:
ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations
Workshop on Frontiers of Extreme Computing Santa Cruz, CA October 24, 2005 ITRS MOSFET Scaling Trends, Challenges, and Key Technology Innovations Peter M. Zeitzoff Outline Introduction MOSFET scaling and
FinFET-based Design for Robust Nanoscale SRAM
FinFET-based Design for Robust Nanoscale SRAM Prof. Tsu-Jae King Liu Dept. of Electrical Engineering and Computer Sciences University of California at Berkeley Acknowledgements Prof. Bora Nikoli Zheng
EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University
TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018
TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 Paper Setter Detail Name Designation Mobile No. E-mail ID Raina Modak Assistant Professor 6290025725 raina.modak@tib.edu.in
CRYSTAL oscillators are widely used to generate precision
440 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 4, APRIL 1999 An Integrated CMOS Micromechanical Resonator High- Oscillator Clark T.-C. Nguyen, Member, IEEE, and Roger T. Howe, Fellow, IEEE Abstract
VLSI Design. Introduction
VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated
ECEN474: (Analog) VLSI Circuit Design Fall 2011
ECEN474: (Analog) VLSI Circuit Design Fall 2011 Lecture 1: Introduction Sebastian Hoyos Analog & Mixed-Signal Center Texas A&M University Analog Circuit Sequence 326 2 Why is Analog Important? [Silva]
Indium Phosphide and Related Materials Selectively implanted subcollector DHBTs
Indium Phosphide and Related Materials - 2006 Selectively implanted subcollector DHBTs Navin Parthasarathy, Z. Griffith, C. Kadow, U. Singisetti, and M.J.W. Rodwell Dept. of Electrical and Computer Engineering,
Lecture #29. Moore s Law
Lecture #29 ANNOUNCEMENTS HW#15 will be for extra credit Quiz #6 (Thursday 5/8) will include MOSFET C-V No late Projects will be accepted after Thursday 5/8 The last Coffee Hour will be held this Thursday
VLSI Design. Introduction
Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo
Switched Capacitor Concepts & Circuits
Switched apacitor oncepts & ircuits Outline Why Switched apacitor circuits? Historical Perspective Basic Building Blocks Switched apacitors as Resistors Switched apacitor Integrators Discrete time & charge
Chapter 2 : Semiconductor Materials & Devices (II) Feb
Chapter 2 : Semiconductor Materials & Devices (II) 1 Reference 1. SemiconductorManufacturing Technology: Michael Quirk and Julian Serda (2001) 3. Microelectronic Circuits (5/e): Sedra & Smith (2004) 4.
IH2655 Design and Characterisation of Nano- and Microdevices. Lecture 1 Introduction and technology roadmap
IH2655 Design and Characterisation of Nano- and Microdevices Lecture 1 Introduction and technology roadmap IH2655 Design and Characterisation of Nano- and Microdevices Introduction to IH2655 Brief historic
EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS
EVALUATION OF RADIATION HARDNESS DESIGN TECHNIQUES TO IMPROVE RADIATION TOLERANCE FOR CMOS IMAGE SENSORS DEDICATED TO SPACE APPLICATIONS P. MARTIN-GONTHIER, F. CORBIERE, N. HUGER, M. ESTRIBEAU, C. ENGEL,
MEMS in ECE at CMU. Gary K. Fedder
MEMS in ECE at CMU Gary K. Fedder Department of Electrical and Computer Engineering and The Robotics Institute Carnegie Mellon University Pittsburgh, PA 15213-3890 fedder@ece.cmu.edu http://www.ece.cmu.edu/~mems
INTRODUCTION TO MOS TECHNOLOGY
INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor
Lecture Wrap up. December 13, 2005
6.012 Microelectronic Devices and Circuits Fall 2005 Lecture 26 1 Lecture 26 6.012 Wrap up December 13, 2005 Contents: 1. 6.012 wrap up Announcements: Final exam TA review session: December 16, 7:30 9:30
ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor
Nanosecond Thermal Processing for Self-Aligned Silicon-on-Insulator Technology
TECHNICAL DOCUMENT 3195 April 2005 Nanosecond Thermal Processing for Self-Aligned Silicon-on-Insulator Technology A. D. Ramirez B. W. Offord J. D. Popp S. D. Russell J. F. Rowland Approved for public release;
Notes. (Subject Code: 7EC5)
COMPUCOM INSTITUTE OF TECHNOLOGY & MANAGEMENT, JAIPUR (DEPARTMENT OF ELECTRONICS & COMMUNICATION) Notes VLSI DESIGN NOTES (Subject Code: 7EC5) Prepared By: MANVENDRA SINGH Class: B. Tech. IV Year, VII
ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices
ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor
Session 3: Solid State Devices. Silicon on Insulator
Session 3: Solid State Devices Silicon on Insulator 1 Outline A B C D E F G H I J 2 Outline Ref: Taurand Ning 3 SOI Technology SOl materials: SIMOX, BESOl, and Smart Cut SIMOX : Synthesis by IMplanted
Lecture Notes 5 CMOS Image Sensor Device and Fabrication
Lecture Notes 5 CMOS Image Sensor Device and Fabrication CMOS image sensor fabrication technologies Pixel design and layout Imaging performance enhancement techniques Technology scaling, industry trends
Jan Bogaerts imec
imec 2007 1 Radiometric Performance Enhancement of APS 3 rd Microelectronic Presentation Days, Estec, March 7-8, 2007 Outline Introduction Backside illuminated APS detector Approach CMOS APS (readout)
Process Technology to Fabricate High Performance MEMS on Top of Advanced LSI. Shuji Tanaka Tohoku University, Sendai, Japan
Process Technology to Fabricate High Performance MEMS on Top of Advanced LSI Shuji Tanaka Tohoku University, Sendai, Japan 1 JSAP Integrated MEMS Technology Roadmap More than Moore: Diversification More
Wiring Parasitics. Contact Resistance Measurement and Rules
Wiring Parasitics Contact Resistance Measurement and Rules Connections between metal layers and nonmetal layers are called contacts. Connections between metal layers are called vias. For non-critical design,
Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor
Aptina MT9P111 5 Megapixel, 1/4 Inch Optical Format, System-on-Chip (SoC) CMOS Image Sensor Imager Process Review For comments, questions, or more information about this report, or for any additional technical
6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators
6.776 High Speed Communication Circuits and Systems Lecture 14 Voltage Controlled Oscillators Massachusetts Institute of Technology March 29, 2005 Copyright 2005 by Michael H. Perrott VCO Design for Narrowband
Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families
1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018
Fin-Shaped Field Effect Transistor (FinFET) Min Ku Kim 03/07/2018 ECE 658 Sp 2018 Semiconductor Materials and Device Characterizations OUTLINE Background FinFET Future Roadmap Keeping up w/ Moore s Law
EECS130 Integrated Circuit Devices
EECS130 Integrated Circuit Devices Professor Ali Javey 11/01/2007 MOSFETs Lecture 5 Announcements HW7 set is due now HW8 is assigned, but will not be collected/graded. MOSFET Technology Scaling Technology
Vibrating MEMS resonators
Vibrating MEMS resonators Vibrating resonators can be scaled down to micrometer lengths Analogy with IC-technology Reduced dimensions give mass reduction and increased spring constant increased resonance
Microelectronics, BSc course
Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT
A New SiGe Base Lateral PNM Schottky Collector. Bipolar Transistor on SOI for Non Saturating. VLSI Logic Design
A ew SiGe Base Lateral PM Schottky Collector Bipolar Transistor on SOI for on Saturating VLSI Logic Design Abstract A novel bipolar transistor structure, namely, SiGe base lateral PM Schottky collector
AE53/AC53/AT53/AE103 ELECT. DEVICES & CIRCUITS DEC 2015
Q.2 a. By using Norton s theorem, find the current in the load resistor R L for the circuit shown in Fig.1. (8) Fig.1 IETE 1 b. Explain Z parameters and also draw an equivalent circuit of the Z parameter
Lecture: Integration of silicon photonics with electronics. Prepared by Jean-Marc FEDELI CEA-LETI
Lecture: Integration of silicon photonics with electronics Prepared by Jean-Marc FEDELI CEA-LETI Context The goal is to give optical functionalities to electronics integrated circuit (EIC) The objectives
In this lecture we will begin a new topic namely the Metal-Oxide-Semiconductor Field Effect Transistor.
Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 38 MOS Field Effect Transistor In this lecture we will begin
Wu Lu Department of Electrical and Computer Engineering and Microelectronics Laboratory, University of Illinois, Urbana, Illinois 61801
Comparative study of self-aligned and nonself-aligned SiGe p-metal oxide semiconductor modulation-doped field effect transistors with nanometer gate lengths Wu Lu Department of Electrical and Computer
Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches
University of Pennsylvania From the SelectedWorks of Nipun Sinha 29 Body-Biased Complementary Logic Implemented Using AlN Piezoelectric MEMS Switches Nipun Sinha, University of Pennsylvania Timothy S.