VLSI Design I; A. Milenkovic 1

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1 E/EE, E 5 VLI Design I L: dder Design Department of Electrical and omputer Engineering University of labama in Huntsville leksandar Milenkovic ( www. ece.uah.edu/~milenka ) www. ece.uah.edu/~milenka/cpe5-f [dapted from Rabaey s Digital Integrated ircuits,, J. Rabaey et al. and Mary Jane Irwin ( www. cse. psu.edu/~mji ) ] ourse dministration Instructor: leksandar Milenkovic milenka@ece.uah.edu EB -L Office Hrs: MW :-: T: Fathima Tareen roject pr.: For schedule Follow conventions for ppt file names Timing, content,... HW#: Due // roject: Reports due // Design submission due // (arrange with instructor & lab instructor) // VLI Design I;. Milenkovic Review: Basic Building Blocks Datapath Execution units dder, multiplier, divider, shifter, etc. Register file and pipeline registers Multiplexers, decoders ontrol Finite state machines (L, ROM, random logic) Interconnect witches, arbiters, buses Memory aches (RMs), TLBs, DRMs, buffers // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

2 in The -bit Binary dder B -bit Full dder (F) out How can we modify it easily to build an adder/subtractor? How can we make it better (faster, lower power, smaller)? B carry status kill kill propagate propagate propagate propagate generate generate &B B B in in K! &!B out &B & in B& in (majority function) & in How can we use it to build a 6-bit adder? // VLI Design I;. Milenkovic in out F ate Level Implementations The way you learned to design in EE and E B in B in t t t t t t out out // VLI Design I;. Milenkovic 5 arry-look -head dder L () Idea: speed up carry computation i i i* i ropagate: i i B i if i, then carry from (i-)th stage is propagated enerate: i i *B i if i there is carry out i i Bi i i B i i i Bi i i i i i i i (i i i) i i i i i i i i i i i (i i i) i i i i i i i i i i // VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic

3 VLI Design I;. Milenkovic // VLI Design I;. Milenkovic arry-look -head dder L () enerator arry enerate Block um enerator B B B B // VLI Design I;. Milenkovic arry-look -head dder L () ) ( ) ( ) ( // VLI Design I;. Milenkovic 9 arry-look -head dder L (5) : B : : - B B B

4 Review: XOR F in B out 6 transistors // VLI Design I;. Milenkovic Review: L F!B B! in in!! B!B in! in B!!B in! in! out out transistors, dual rail beware of threshold drops // VLI Design I;. Milenkovic Delay Balanced F B!B in! Identical Delays for arry and um B p! out in in!b!!! eration ignal set-up transistors arry generation // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

5 Review: Mirror dder transistors B B B B in -propagate kill 6 6 in! out in 6! -propagate generate in B B B in B out &B B& in & in UM &B& in OUT &( B in ) izing: Each input in the carry circuit has a logical effort of so the optimal fan-out for each is also. ince! out drives internal and inverter transistor gates (to form in for the nms bit adder) should oversize the carry circuit. MO/NMO ratio of. // VLI Design I;. Milenkovic Mirror dder Features The NMO and MO chains are completely symmetrical with a maximum of two series transistors in the carry circuitry,guaranteeing identical rise and fall transitions if the NMO and MO devices are properly sized. When laying out the cell, the most critical issue is the minimization of the capacitances at node! out (four diffusion capacitances, two internal gate capacitances, and two inverter gate capacitances). hared diffusions can reduce the stack node capacitances. The transistors connected to in are placed closest to the output. Only the transistors in the carry stage have to be optimized for optimal speed. ll transistors in the sum stage can be minimal size. // VLI Design I;. Milenkovic 6-bit dder/ubtractor Ripple arry dder (R) built out of 6 Fs ubtraction complement all subtrahend bits (xor gates) and set the low order carry-in R advantage: simple logic, so small (low cost) disadvantage: slow (O(N) for N bits) and lots of glitching (so lots of energy consumption) add/subt B B B B 6 6 in -bit F -bit F -bit F bit F 6 6 out // VLI Design I;. Milenkovic 5 VLI Design I;. Milenkovic 5

6 Ripple arry dder (R) B B B B out F F F F in T adder T F (,B out ) (N-)T F ( in out ) T F ( in ) T O(N) worst case delay Real oal: Make the fastest possible carry path // VLI Design I;. Milenkovic 6 Inversion roperty Inverting all inputs to a F results in inverted values for all outputs B B out F in out F in! (, B, in ) (!,!B,! in )! out (, B, in ) out (!,!B,! in ) // VLI Design I;. Milenkovic Exploiting the Inversion roperty B B B B out F F F F in inverted cell regular cell Minimizes the critical path (the carry chain) by eliminating inverters between the Fs (will need to increase the transistor sizing on the carry chain portion of the mirror adder). Now need two flavors of Fs // VLI Design I;. Milenkovic VLI Design I;. Milenkovic 6

7 Fast arry hain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated i i & B i i B i propagated i i B i (sometimes use i B i ) annihilated (killed) K i! i &!B i iving a carry recurrence of i i i i // VLI Design I;. Milenkovic 9 Fast arry hain Design The key to fast addition is a low latency carry network What matters is whether in a given position a carry is generated i i & B i i B i propagated i i B i (sometimes use i B i ) annihilated (killed) K i! i &!B i iving a carry recurrence of i i i i // VLI Design I;. Milenkovic Manchester arry hain witches controlled by i and i! i i i! i clk Total delay of time to form the switch control signals i and i setup time for the switches signal propagation delay through N switches in the worst case // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

8 -bit liced M dder B B B B clk & & & &!!!!! // VLI Design I;. Milenkovic Domino Manchester arry hain ircuit clk i, i, clk!( i, )!( i, )!( i, )!( i, ) // VLI Design I;. Milenkovic Binary dder Landscape synchronous word parallel adders ripple carry adders (R) T O(N), O(N) carry prop min adders signed-digit fast carry prop residue adders adders adders T O(), O(N) Manchester carry parallel conditional carry carry chain select prefix sum skip T O(N) O(N) T O(log N) O(N log N) T O( N), O(N) // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

9 arry-kip (arry-bypass) dder B B B B o, F F F F i, o, B Block ropagate If ( & & & ) then o, i, otherwise the block itself kills or generates the carry internally // VLI Design I;. Milenkovic 5 arry-kip hain Implementation carry-out block carry-out B block carry-in! out in B // VLI Design I;. Milenkovic 6 -bit Block arry-kip dder bits to 5 bits to bits to bits to arry ropagation arry ropagation arry ropagation arry ropagation i, um um um um Worst-case delay carry from bit to bit 5 carry generated in bit, ripples through bits,, and, skips the middle two groups (B is the group size in bits), ripples in the last group from bit to bit 5 T add t setup B t carry ((N/B) -) t skip B t carry t sum // VLI Design I;. Milenkovic VLI Design I;. Milenkovic 9

10 Optimal Block ize and Time ssuming one stage of ripple (t carry ) has the same delay as one skip logic stage (t skip ) and both are T k B (N/B-) B t setup ripple in skips ripple in t sum block last block B N/B o the optimal block size, B, is dt k /db (N/) B opt nd the optimal time is Optimal T k ( (N)) // VLI Design I;. Milenkovic Variable block sizes arry-kip dder Extensions carry that is generated in, or absorbed by, one of the inner blocks travels a shorter distance through the skip blocks, so can have bigger blocks for the inner carries without increasing the overall delay out in Multiple levels of skip logic out in skip level skip level ND of the first level skip signals (B s) // VLI Design I;. Milenkovic 9 arry-kip dder omparisons 6 5 B B B B5 B6 R k Vk bits 6 bits bits bits 6 bits // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

11 arry elect dder s B s recompute the carry out of each block for both carry_in and carry_in (can be done for all blocks in parallel) and then select the correct one out -b s s carry propagation carry propagation multiplexer s eration in // VLI Design I;. Milenkovic arry elect dder: ritical ath bits to 5 bits to bits to bits to s s s s s s s s carry carry carry carry carry carry carry carry out s s s s in // VLI Design I;. Milenkovic arry elect dder: ritical ath bits to 5 bits to bits to bits to s s s s s s s s carry carry carry carry carry carry carry carry out s s s s in T add t setup B t carry N/B t t sum // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

12 quare Root arry elect dder s bits to B s 9 bits 9 to bits 5 to bits to bits to s s s s s s s s s s carry carry carry carry carry carry carry carry carry carry out s s s s in s // VLI Design I;. Milenkovic quare Root arry elect dder s bits to B s 9 bits 9 to bits 5 to bits to s Bs bits to s B s s s s s s s s s s s carry 6 carry carry 5 carry carry carry carry carry carry carry out s um gen s s s in s T add t setup t carry vn t t sum // VLI Design I;. Milenkovic 5 arallel refix dders (s) Define carry operator on (,) signal pairs (, ) (, ) where (,)! is associative, i.e., [(g,p ) (g,p )] (g,p ) (g,p ) [(g,p ) (g,p )] // VLI Design I;. Milenkovic 6 VLI Design I;. Milenkovic

13 arallel refix omputation T log N - log N T log N arallel refix omputation T log N - log N T log N eneral tructure iven and terms for each bit position, computing all the carries is equal to finding all the prefixes in parallel (, ) (, ) (, ) ( N-, N- ) ( N-, N- ) ince is associative, we can group them in any order but note that it is not commutative i, i logic ( unit delay) i parallel prefix logic tree ( unit delay per level) i logic ( unit delay) Measures to consider number of cells tree cell depth (time) tree cell area cell fan-in and fan-out max wiring length wiring congestion delay path variation (glitching) // VLI Design I;. Milenkovic Brent-Kung 5 p 5 p p 9 p p p in N/ 6 5 // VLI Design I;. Milenkovic Brent-Kung 5 p 5 p p 9 p p p in N/ 6 5 // VLI Design I;. Milenkovic 9 VLI Design I;. Milenkovic

14 arallel refix omputation T log N log N Kogge-tone F dder in N 6 5 T add t setup log N t t sum // VLI Design I;. Milenkovic 6 More dder omparisons 5 R k Vk K bits 6 bits bits bits 6 bits // VLI Design I;. Milenkovic dder peed omparisons 6 5 R M k Vk l B&K 6 bits bits 6 bits // VLI Design I;. Milenkovic VLI Design I;. Milenkovic

15 5 dder verage ower omparisons 5 5 R M k Vk l B&K 5 6 bits bits 6 bits // VLI Design I;. Milenkovic D of dder omparisons 6 R M k Vk l BK bits 6 bits bits bits 6 bits From Nagendra, 996 // VLI Design I;. Milenkovic VLI Design I;. Milenkovic 5