Spiral Content Mapping. Spiral 1 / Unit 8. Outcomes DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates

Size: px
Start display at page:

Download "Spiral Content Mapping. Spiral 1 / Unit 8. Outcomes DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates"

Transcription

1 Spiral ontent Mapping Spiral Theory ombinational esign Sequential esign System Level esign Implementation and Tools Project Spiral 1 / Unit 8 Transistor Implementations MOS Logic Gates Performance 1 metrics (latency vs. throughput) oolean lgebra (Pt. 1) anonical Representations 2 oolean algebra for analysis and optimization (emorgan's theorem) ecoders and muxes Synthesis with min/maxterms Synthesis with Karnaugh Maps Synthesis with memory dder and comparator design Edge triggered flip flops Registers (with enables) istables, latches, and Flipflops ounters Memories Encoded State machine design One hot state machine design ontrol and datapath decomposition Single cycle PU Structural Verilog HL MOS gate implementation Fabrication process MOS Theory apacitance, delay and sizing Memory constructs 3 Shannon's theorem Synthesis with muxes (Shannon's theorem) HW/SW partitioning us interfacing Power and other logic families E design process Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand latency, throughput, and at least 1 technique to improve throughput I can identify when I need state vs. a purely combinational function I can convert a simple word problem to a logic function (TT or canonical form) or state diagram I can use Karnaugh maps to synthesize combinational functions with several outputs I can design a working state machine given a state diagram I can implement small logic functions with complex MOS gates EMORGN'S THEOREM

2 emorgan s Theorem Generalized emorgan s Theorem F (X 1,,X n,, ) = F(X 1,,X n,,) F = (XY) Z (YW) To find F, invert both sides of the equation and then use emorgan s theorem to simplify To find F, swap N s and OR s and complement each literal. However, you must maintain the original order of operations. F = (XY) Z (YW) F = (XY) (Z (YW)) F = (X Y) (Z (YW)) Note: This parentheses doesn t matter (we are just OR ing X, Y, and the following subexpression) F = (XY) Z (YW) F = XY (Z (YW)) Fully parenthesized to show original order of ops. F = (X Y) (Z (Y W)) F = X Y (Z (Y W)) N s & OR s swapped Each literal is inverted emorgan s Theorem Example ancel as many bubbles as you can using emorgan s theorem. With focus on MOS Transistors SEMIONUTOR TEHNOLOGY

3 Evolution of transistor in Is Invention of the Transistor JT invention, ell Labs, 1947 Single transistor, TI, 1958 Vacuum tubes ruled in first half of 20 th century Large, expensive, power hungry, unreliable MOS gate, Fairchild, 1963 First processor, Intel, 1970 Very Large Scale Integration, 1978 Up to 20k transistor Ultra Large Scale Integration, : first point contact transistor John ardeen and Walter rattain at ell Labs See rystal Fire by Riordan, Hoddeson More than 1 million per chip System on hip, Millions to several billion transistors Growth Rate Minimum Feature Size % compound annual growth rate over 50 years No other technology has grown so fast so long riven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society [Moore65] Electronics Magazine

4 Intel 4004 Micro Processor Intel ore I transistors 1 MHz operation 2 nd Gen. Intel ore i7 Extreme Processor for desktops launched in Q4 of 2012 #cores/#threads: 6/12 Technology node: 32nm lock speed: 3.5 GHz Transistor count: Over one billion ache: 15M ddressable memory: 64G Size: 52.5mm by 45.0mm mm 2 RM ortex ortex RM ortex 15 in 2011 to cores per cluster, two clusters per chip Technology node: 22nm lock speed: 2.5 GHz Transistor count: Over one billion ache: Up to 4M per cluster ddressable memory: up to 1T Size: 52.5mm by 45.0mm 15

5 IM z13 Storage ontroller nnual Sales >10 19 transistors manufactured in billion for every human on the planet ost per Transistor Internet Traffic Growth cost: pertransistor Fabrication capital cost per transistor (Moore s law)

6 TRNSISTOR SIS Transistors s Switches Transistor act as a form of switch (on / off) ifferent physical structures lead to different kinds of transistors ipolar Junction Transistor (JT) Initial technology back in the late 40's 60's Metal Oxide Semiconductor Field Effect Transistor (MOSFET) ominates the digital I market today ll transistors essentially function similarly with 3 nodes/terminals: 1 node serves as the switch value allowing current to flow between the other 2 nodes (on) or preventing current flow between the other 2 nodes (off) Example: if the switch input voltage is 5V, then current is allowed to flow between the other nodes Switch Input (Hi or Lo Voltage) urrent can flow based on voltage of input switch Semiconductors Semiconductor Material Semiconductor material is not a great conductor material in its pure form Small amount of free charge an be implanted ( doped ) with other elements (e.g. boron or arsenic) to be more conductive Increases the amount of free charge Pure Silicon PType Silicon (oped with boron) Electron acceptors NType Silicon (oped with arsenic) Electron donors

7 Silicon Lattice and opant toms Pure silicon: 3 lattice of atoms (a cubic crystal) and a poor conductor onductivity can be raised by adding either donors or acceptor onors: Group V dopant impurities, which have more free electrons than silicon The resulting material is called n type Group III dopants impurities which have lack of electrons The resulting material is called p type Transistor Types ipolar Junction Transistors (JT) npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector However the fact that it requires a current into the base means it burns power (P = I*V) and thus limits how many we can integrate on a chip (i.e. density) Metal Oxide Semiconductor Field Effect Transistors nmos and pmos MOSFETS Voltage applied to insulated gate controls current between source and drain Gate input requires no constant current thus low power! We will focus on MOSFET in this class emitter Source ptype ntype ptype base conductive polysilicon ptype Gate Input collector npn JT Ntype MOSFET rain ntype NMOS Transistor Physics Transistor is started by implanting two n type silicon areas, separated by p type Source Input W ptype silicon ( extra positive charges) L ntype silicon (extra negative charges) rain Input 18.28

8 NMOS Transistor Physics NMOS Transistor Physics thin, insulator layer (silicon dioxide or just oxide ) is placed over the silicon between source and drain thin, insulator layer (silicon dioxide or just oxide ) is placed over the silicon between source and drain onductive polysilicon material is layered over the oxide to form the gate input Source Input rain Output Source Input Gate Input rain Output conductive polysilicon Insulator Layer (oxide) ntype silicon (extra negative charges) Insulator Layer (oxide) ntype silicon (extra negative charges) ptype silicon ( extra positive charges) ptype silicon ( extra positive charges) NMOS Transistor Physics NMOS Transistor Physics Positive voltage (charge) at the gate input repels the extra positive charges in the p type silicon Result is a negativecharge channel between the source input and drain Source Input negativelycharge channel Gate Input positive charge repelled ptype rain Output ntype Electrons can flow through the negative channel from the source input to the drain output The transistor is on Source Input Gate Input Negative channel between source and drain = urrent flow ptype rain Output ntype

9 NMOS Transistor Physics If a low voltage (negative charge) is placed on the gate, no channel will develop and no current will flow The transistor is off Source Input Gate Input No negative channel between source and drain = No current flow ptype rain Output ntype PMOS vs. NMOS PMOS transistors can also be made that are on when the gate voltage is low and off when it is high Source Input Gate Input Negative channel between source and drain = urrent flow ptype rain Output ntype Source Input Gate Input "Positive" channel between source and drain = urrent flow ntype ptype NMOS PMOS NMOS and PMOS Transistors NMOS conducts when gate input is at a high voltage (logic 1 ) NMOS Transistors Understanding physical constraints MOS TRNSISTOR LEVEL IMPLEMENTTION PMOS conducts when gate input is at a low voltage (logic 0 ) Indicates a Ptype urrent Flows (Small resistance between source and output ) NMOS (On if G=1) PMOS Transistors 0 1 urrent Flows (Small resistance between source and output) No urrent Flows (Large resistance between source and output ) No urrent Flows (Large resistance between source and output) PMOS (On if G=0)

10 NMOS Transistors in Series/Parallel onnection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high PMOS Transistors in Series/Parallel onnection PMOS switch closes when switch control input is low 1 F F = 1 if N = F F = 1 if and 1 F F = 1 if OR = 1 F F = 1 if OR We ll Have Our Strengths NMOS and PMOS Transistors NMOS are: Good at pulling the output voltage OWN to 0 ad at pulling the output voltage up to 1 PMOS are: NMOS PMOS Good at pulling the output voltage up to 1 ad at pulling the output voltage down to 0 GN Vdd Source Source Gate Gate rain rain 0 Vdd Vdd GN rain rain Gate Gate Source Source < Vdd > 0 NMOS transistors work best when one terminal is connected to a low voltage source, pulling the other terminal down to that voltage Normally, source terminal is connected to GN=0V PMOS transistors work best when one terminal is connected to a high voltage source, pulling the other terminal down to that voltage Normally, source terminal is connected to power supply voltage (5V, 3V, etc.) 0V NMOS 3V PMOS

11 MOS Signal Strength omplimentary MOS (MOS) Use PMOS to connect output to high voltage source We call this the Pull Up Network Use NMOS to connect output to low voltage source (usually = GN) We call this the Pull own Network Either PMOS or NMOS should create a conductive path to output, but not both Pullup OFF Pullup ON Pulldown OFF Z (float) 1 Inputs PullUp Network Pullown Network PMOS Output NMOS Strength of signal How close it approximates ideal voltage source V and GN rails are strongest 1 and 0 nmos passes strong 0 ut degraded or weak 1 pmos passes strong 1 ut degraded or weak 0 Thus nmoses are best for the pull down network, pmoses are best for the pull up network Pulldown ON 0 X (crowbar) MOS Inverter Inverter can be formed using one PMOS and NMOS transistor The input value connects to both gate inputs The output is formed at the junction of the drains MOS Inverter When input is 1, NMOS conducts and output is pulled down to 0V (GN) When input is 0, PMOS conducts and output is pulled up to 3V (V )

12 MOS NN Gate MOS N Gate If and = 1, the output of the first circuit is pulled to 0 (opposite of N function) If or = 0, the output of the first circuit is pulled to 1 (opposite of N function) Rule of onduction omplements Pull up network is the dual (complement) of pull down Parallel > series, series > parallel NN If and = 1, the output of the first circuit is pulled to 0 (opposite of N function) If or = 0, the output of the first circuit is pulled to 1 (opposite of N function) Inverter is then used to produce true N output NN Inverter to produce N MOS NOR Gate MOS NOR Gate If or = 1, the output of the first circuit is pulled to 0 (opposite of OR function) If and = 0, the output of the circuit is pulled to 1 (opposite of OR function) Rule of onduction omplements Pull up network is the dual (complement) of pull down Parallel > series, series > parallel NOR If or = 1, the output of the first circuit is pulled to 0 (opposite of OR function) If and = 0, the output of the circuit is pulled to 1 (opposite of OR function) Inverter is then used to produce true OR output OR

13 ompound Gates How could you build this gate? You could try building each gate separately Two N gates = 2*6 transistors One NOR gate = 4 transistors With emorgan's Two NN gates = 2*4 transistors One N gate = 6 transistors Or you could take build it as a single compound gate F F ompound Gates ompound gates can do any inverting function Ex: N OR INVERT (OI) Full Gate Separate (a) (e) Y = Separate Separate '' Separate (c) '' Y (b) (d) (f) ('')('') Y PN PUN ompound Gate pproach ompound Gate Example For an inverting function just look at the expression (w/o the inversion) and Implement the PN using: Series connections for N Parallel connections for OR Implement PUN as dual of PN Swap series and parallel If function is non inverting just add an inverter at the output Y = ( ) Y

14 ompound Gate Example ompound Gate Example (cont.) This is really a MOS inverter (2 transistors) but we just show it this way to save space and focus on the 1 st stage cell OUT = ( ) OUT = ( ) nother ompound Gate Example OUT = ( E) OUT = ( E) dd an inverter at the output Implement inverting function using compound MOS gate uild a 2 to 1 mux at the Transistor Level I 0 I 1 Y? S Vdd OR apply emorgan's theorem with the inner inversion and just build the resulting circuit Vdd S Vdd I1 Vdd E Vdd S S S I0 Y OUT S S I0 I1 E

15 18.57 MOS Layout Structure FRITION L: hannel Length W: hannel Width Layout cross section MOS Layout Structure Layers Schematic oth n channel (NMOS) and p channel (PMOS) transistors are built on the same chip substrate Well: special region created in which the semiconductor type is opposite the substrate s type Example: n well MOS fabrication technology to create a n type substrate inside the already p type substrate The n well is used to create the PMOS transistors Start from the bottom up uild the n and p type material areas on the silicon Lay the insulator layer (oxide) over the silicon Place the polysilicon (gate) on top of the oxide onnect wires to the source, gate, and drain use layers of metal above the gate 2 Layers of Metal Wires Transistor 1 Transistor 2 Side View Transistor 1 Transistor 2 Top View

16 Photolithography n I consists of several layers of material that are manufactured in successive steps Lithography is used to selectively process the layers where the 2 mask geometry is copied on the surface Once the desired shape is patterned with photoresist the unprotected areas are etched away Lift off and etching are different techniques to remove and shape Photolithography Expose only specific areas of the chip for layer deposition or etching layer of photoresist material is deposited on the chip Photoresist becomes soluble when exposed to ultraviolet light Using a mask to cast a shadow, some portions of photoresist can be kept while the remainder is washed away Photoresist covering silicon surface Photolithography Ion Implantation Expose only specific areas of the chip for layer deposition or etching layer of photoresist material is deposited on the chip Photoresist becomes soluble when exposed to ultraviolet light Using a mask to cast a shadow, some portions of photoresist can be kept while the remainder is washed away Ultraviolet Light Exposed area will become soluble and be washed away exposing the surface underneath Mask creating shadow Photoresist covering silicon surface Masked area will stay hardened and protect the surface underneath fter washing away soluble photoresist, silicon in the shape of the mask is exposed an be implanted with ions to make n or p type material Exposed area can now be implanted with dopants Ion source bombards the exposed silicon Photoresist covering silicon surface Surface still covered by photoresist will be protected from ion implantation

17 Resulting Material Layer eposition fter implantation, remaining photoresist can be exposed and washed away leaving n type silicon in the appropriate areas For layers above the surface (oxide, gate polysilicon, and metal wires), a similar but slightly different process is used 1. Entire layer of material is deposited over entire area 2. overed with photoresist 3. Mask is used to indicate where material is desired Ultraviolet Light Photoresist layer is placed on top Mask desired material areas ntype doped silicon Oxide layer placed over entire chip area Layer eposition Layer eposition For layers above the surface (oxide, gate polysilicon, and metal wires), a similar but slightly different process is used 1. Entire layer of material is deposited over entire chip 2. overed with photoresist 3. Mask is used to indicate where material is desired 4. Wash away exposed photoresist 5. Use chemical/mechanical etching process to remove exposed oxide Etching process removes exposed oxide material but cannot penetrate photoresist material For layers above the surface (oxide, gate polysilicon, and metal wires), a similar but slightly different process is used 1. Entire layer of material is deposited over entire chip 2. overed with photoresist 3. Mask is used to indicate where material is desired 4. Wash away exposed photoresist 5. Use chemical/mechanical etching process to remove exposed oxide 6. Remaining photoresist can be removed exposing oxide in the desired location Oxide layer for gate input Oxide layer placed over entire chip area

18 Layer eposition Simplified MOS Fabrication Process Process is repeated for gate (polysilicon) and metal wire layers separate mask is required for each layer to indicate where the substance should be kept and where it should be etched away Fabrication Images mageservice/rticleimage/2003/n/b208563c/b208563cf1.gif

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates

Outcomes. Spiral 1 / Unit 8. DeMorgan s Theorem DEMORGAN'S THEOREM. Transistor Implementations CMOS Logic Gates 18.1 18.2 Spiral 1 / Unit 8 Transistor Implementations MOS Logic Gates Mark Redekopp Outcomes I know the difference between combinational and sequential logic and can name examples of each. I understand

More information

Spiral 1 / Unit 8. Transistor Implementations CMOS Logic Gates

Spiral 1 / Unit 8. Transistor Implementations CMOS Logic Gates 18.1 Spiral 1 / Unit 8 Transistor Implementations CMOS Logic Gates 18.2 Spiral Content Mapping Spiral Theory Combinational Design Sequential Design System Level Design Implementation and Tools Project

More information

VLSI Design. Introduction

VLSI Design. Introduction VLSI Design Introduction Outline Introduction Silicon, pn-junctions and transistors A Brief History Operation of MOS Transistors CMOS circuits Fabrication steps for CMOS circuits Introduction Integrated

More information

VLSI Design. Introduction

VLSI Design. Introduction Tassadaq Hussain VLSI Design Introduction Outcome of this course Problem Aims Objectives Outcomes Data Collection Theoretical Model Mathematical Model Validate Development Analysis and Observation Pseudo

More information

+1 (479)

+1 (479) Introduction to VLSI Design http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable

More information

420 Intro to VLSI Design

420 Intro to VLSI Design Dept of Electrical and Computer Engineering 420 Intro to VLSI Design Lecture 0: Course Introduction and Overview Valencia M. Joyner Spring 2005 Getting Started Syllabus About the Instructor Labs, Problem

More information

Lecture 0: Introduction

Lecture 0: Introduction Lecture 0: Introduction Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor Fast, cheap, low power

More information

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng

EE4800 CMOS Digital IC Design & Analysis. Lecture 1 Introduction Zhuo Feng EE4800 CMOS Digital IC Design & Analysis Lecture 1 Introduction Zhuo Feng 1.1 Prof. Zhuo Feng Office: EERC 730 Phone: 487-3116 Email: zhuofeng@mtu.edu Class Website http://www.ece.mtu.edu/~zhuofeng/ee4800fall2010.html

More information

Layers. Layers. Layers. Transistor Manufacturing COMP375 1

Layers. Layers. Layers. Transistor Manufacturing COMP375 1 VLSI COMP375 Computer Architecture Middleware other CS classes Machine Language Microcode Logic circuits Transistors Middleware Machine Language - earlier Microcode Logic circuits Transistors Middleware

More information

Topic 3. CMOS Fabrication Process

Topic 3. CMOS Fabrication Process Topic 3 CMOS Fabrication Process Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk Lecture 3-1 Layout of a Inverter

More information

Learning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES

Learning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES 26.1 26.2 Learning Outcomes Spiral 26 Semiconductor Material MOS Theory I underst why a diode conducts current under forward bias but does not under reverse bias I underst the three modes of operation

More information

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o.

Layout of a Inverter. Topic 3. CMOS Fabrication Process. The CMOS Process - photolithography (2) The CMOS Process - photolithography (1) v o. Layout of a Inverter Topic 3 CMOS Fabrication Process V DD Q p Peter Cheung Department of Electrical & Electronic Engineering Imperial College London v i v o Q n URL: www.ee.ic.ac.uk/pcheung/ E-mail: p.cheung@ic.ac.uk

More information

ENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph

ENG2410 Digital Design CMOS Technology. Fall 2017 S. Areibi School of Engineering University of Guelph ENG2410 Digital Design CMOS Technology Fall 2017 S. reibi School of Engineering University of Guelph The Transistor Revolution First transistor Bell Labs, 1948 Bipolar logic 1960 s Intel 4004 processor

More information

Layers. Layers. Layers. Transistor Manufacturing COMP375 1

Layers. Layers. Layers. Transistor Manufacturing COMP375 1 Layers VLSI COMP370 Intro to Computer Architecture t Applications Middleware other CS classes High level languages Machine Language Microcode Logic circuits Gates Transistors Silicon structures Layers

More information

Unit 3 Digital Circuits (Logic)

Unit 3 Digital Circuits (Logic) Unit 3 Digital Circuits (Logic) 1 2 A Brief History COMPUTERS AND SWITCHING TECHNOLOGY 3 Mechanical Computers Primarily gearbased Difference Engine and Analytic Engine designed and partially implemented

More information

Basic Fabrication Steps

Basic Fabrication Steps Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor

More information

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs

CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs CMOS Digital Integrated Circuits Lec 2 Fabrication of MOSFETs 1 CMOS Digital Integrated Circuits 3 rd Edition Categories of Materials Materials can be categorized into three main groups regarding their

More information

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02

EE 5611 Introduction to Microelectronic Technologies Fall Thursday, September 04, 2014 Lecture 02 EE 5611 Introduction to Microelectronic Technologies Fall 2014 Thursday, September 04, 2014 Lecture 02 1 Lecture Outline Review on semiconductor materials Review on microelectronic devices Example of microelectronic

More information

INTRODUCTION TO MOS TECHNOLOGY

INTRODUCTION TO MOS TECHNOLOGY INTRODUCTION TO MOS TECHNOLOGY 1. The MOS transistor The most basic element in the design of a large scale integrated circuit is the transistor. For the processes we will discuss, the type of transistor

More information

CMOS Technology. 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates. Handouts: Lecture Slides. metal ndiff.

CMOS Technology. 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates. Handouts: Lecture Slides. metal ndiff. CMOS Technology 1. Why CMOS 2. Qualitative MOSFET model 3. Building a MOSFET 4. CMOS logic gates poly pdiff metal ndiff Handouts: Lecture Slides L03 - CMOS Technology 1 Building Bits from Atoms V in V

More information

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.

Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-

More information

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics

Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1. Topics Chapter 3: Basics Semiconductor Devices and Processing 2006/9/27 1 Topics What is semiconductor Basic semiconductor devices Basics of IC processing CMOS technologies 2006/9/27 2 1 What is Semiconductor

More information

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag FABRICATION OF CMOS INTEGRATED CIRCUITS Dr. Mohammed M. Farag Outline Overview of CMOS Fabrication Processes The CMOS Fabrication Process Flow Design Rules Reference: Uyemura, John P. "Introduction to

More information

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT

Learning Outcomes. Spiral 2 8. Digital Design Overview LAYOUT 2-8.1 2-8.2 Spiral 2 8 Cell Mark Redekopp earning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as

More information

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices

ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor

More information

VLSI Design. Static CMOS Logic

VLSI Design. Static CMOS Logic VLSI esign Static MOS Logic [dapted from Rabaey s igital Integrated ircuits, 2002, J. Rabaey et al.] EE4121 Static MOS Logic.1 ZLM Review: MOS Process at a Glance efine active areas Etch and fill trenches

More information

ECE520 VLSI Design. Lecture 11: Combinational Static Logic. Prof. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 11: Combinational Static Logic. Prof. Payman Zarkesh-Ha EE520 VLSI esign Lecture 11: ombinational Static Logic Prof. Payman Zarkesh-Ha Office: EE ldg. 230 Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 eview of Last

More information

Chapter 3 Basics Semiconductor Devices and Processing

Chapter 3 Basics Semiconductor Devices and Processing Chapter 3 Basics Semiconductor Devices and Processing 1 Objectives Identify at least two semiconductor materials from the periodic table of elements List n-type and p-type dopants Describe a diode and

More information

Design cycle for MEMS

Design cycle for MEMS Design cycle for MEMS Design cycle for ICs IC Process Selection nmos CMOS BiCMOS ECL for logic for I/O and driver circuit for critical high speed parts of the system The Real Estate of a Wafer MOS Transistor

More information

CS8803: Advanced Digital Design for Embedded Hardware

CS8803: Advanced Digital Design for Embedded Hardware HPTER II-6 MO MO WITHE WITH NETWORK -WITHE IN ERIE -WITHE IN PRLLEL -INPUT ELETOR 883: dvanced Digital Design for Embedded Hardware Lecture : MO Transistors and Layout The idea is to use the series and

More information

Notes. (Subject Code: 7EC5)

Notes. (Subject Code: 7EC5) COMPUCOM INSTITUTE OF TECHNOLOGY & MANAGEMENT, JAIPUR (DEPARTMENT OF ELECTRONICS & COMMUNICATION) Notes VLSI DESIGN NOTES (Subject Code: 7EC5) Prepared By: MANVENDRA SINGH Class: B. Tech. IV Year, VII

More information

Semiconductor Physics and Devices

Semiconductor Physics and Devices Metal-Semiconductor and Semiconductor Heterojunctions The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is one of two major types of transistors. The MOSFET is used in digital circuit, because

More information

Lecture 0: Introduction

Lecture 0: Introduction Introduction to CMOS VLSI Design Lecture : Introduction David Harris Steven Levitan Harvey Mudd College University of Pittsburgh Spring 24 Fall 28 Administrivia Professor Steven Levitan TA: Bo Zhao Syllabus

More information

Computer Architecture (TT 2012)

Computer Architecture (TT 2012) Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture

More information

Student Lecture by: Giangiacomo Groppi Joel Cassell Pierre Berthelot September 28 th 2004

Student Lecture by: Giangiacomo Groppi Joel Cassell Pierre Berthelot September 28 th 2004 Student Lecture by: Giangiacomo Groppi Joel Cassell Pierre Berthelot September 28 th 2004 Lecture outline Historical introduction Semiconductor devices overview Bipolar Junction Transistor (BJT) Field

More information

EMT 251 Introduction to IC Design

EMT 251 Introduction to IC Design EMT 251 Introduction to IC Design (Pengantar Rekabentuk Litar Terkamir) Semester II 2011/2012 Introduction to IC design and Transistor Fundamental Some Keywords! Very-large-scale-integration (VLSI) is

More information

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2)

2009 Spring CS211 Digital Systems & Lab 1 CHAPTER 3: TECHNOLOGY (PART 2) 1 CHAPTER 3: IMPLEMENTATION TECHNOLOGY (PART 2) Whatwillwelearninthischapter? we learn in this 2 How transistors operate and form simple switches CMOS logic gates IC technology FPGAs and other PLDs Basic

More information

Microelectronics, BSc course

Microelectronics, BSc course Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT

More information

Newer process technology (since 1999) includes :

Newer process technology (since 1999) includes : Newer process technology (since 1999) includes : copper metalization hi-k dielectrics for gate insulators si on insulator strained silicon lo-k dielectrics for interconnects Immersion lithography for masks

More information

ECE 2300 Digital Logic & Computer Organization

ECE 2300 Digital Logic & Computer Organization ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits

More information

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 7. LECTURE: LOGIC CIRCUITS II: FET, MOS AND CMOS

DIGITAL TECHNICS II. Dr. Bálint Pődör. Óbuda University, Microelectronics and Technology Institute 7. LECTURE: LOGIC CIRCUITS II: FET, MOS AND CMOS DIGITL TECHNICS II Dr. álint Pődör Óbuda University, Microelectronics and Technology Institute 7. LECTURE: LOGIC CIRCUITS II: FET, MOS ND CMOS 2nd (Spring) term 2015/2016 1 7. LECTURE: LOGIC CIRCUITS II:

More information

VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN

VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN VLSI DESIGN AUTOMATION COURSE NOTES THE PRINCIPLES OF VLSI DESIGN Peter M. Maurer ENG 118 Department of Computer Science & Engineering University of South Florida Tampa, FL 33620 1. The Nature of licon

More information

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018

TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 TECHNO INDIA BATANAGAR (DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING) QUESTION BANK- 2018 Paper Setter Detail Name Designation Mobile No. E-mail ID Raina Modak Assistant Professor 6290025725 raina.modak@tib.edu.in

More information

Synthesis of Combinational Logic

Synthesis of Combinational Logic Synthesis of ombinational Logic 6.4 Gates F = xor Handouts: Lecture Slides, PS3, Lab2 6.4 - Spring 2 2/2/ L5 Logic Synthesis Review: K-map Minimization ) opy truth table into K-Map 2) Identify subcubes,

More information

BICMOS Technology and Fabrication

BICMOS Technology and Fabrication 12-1 BICMOS Technology and Fabrication 12-2 Combines Bipolar and CMOS transistors in a single integrated circuit By retaining benefits of bipolar and CMOS, BiCMOS is able to achieve VLSI circuits with

More information

2.8 - CMOS TECHNOLOGY

2.8 - CMOS TECHNOLOGY CMOS Technology (6/7/00) Page 1 2.8 - CMOS TECHNOLOGY INTRODUCTION Objective The objective of this presentation is: 1.) Illustrate the fabrication sequence for a typical MOS transistor 2.) Show the physical

More information

Introduction. Reading: Chapter 1. Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi.

Introduction. Reading: Chapter 1. Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi. Introduction Reading: Chapter 1 Courtesy of Dr. Dansereau, Dr. Brown, Dr. Vranesic, Dr. Harris, and Dr. Choi http://csce.uark.edu +1 (479) 575-6043 yrpeng@uark.edu Why study logic design? Obvious reasons

More information

Introduction to VLSI ASIC Design and Technology

Introduction to VLSI ASIC Design and Technology Introduction to VLSI ASIC Design and Technology Paulo Moreira CERN - Geneva, Switzerland Paulo Moreira Introduction 1 Outline Introduction Is there a limit? Transistors CMOS building blocks Parasitics

More information

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families

Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1 Module-3: Metal Oxide Semiconductor (MOS) & Emitter coupled logic (ECL) families 1. Introduction 2. Metal Oxide Semiconductor (MOS) logic 2.1. Enhancement and depletion mode 2.2. NMOS and PMOS inverter

More information

PHYS 3050 Electronics I

PHYS 3050 Electronics I PHYS 3050 Electronics I Chapter 4. Semiconductor Diodes and Transistors Earth, Moon, Mars, and Beyond Dr. Jinjun Shan, Associate Professor of Space Engineering Department of Earth and Space Science and

More information

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits

ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized

More information

Semiconductor Diodes

Semiconductor Diodes Semiconductor Diodes A) Motivation and Game Plan B) Semiconductor Doping and Conduction C) Diode Structure and I vs. V D) Diode Circuits Reading: Schwarz and Oldham, Chapter 13.1-13.2 Motivation Digital

More information

EC0306 INTRODUCTION TO VLSI DESIGN

EC0306 INTRODUCTION TO VLSI DESIGN EC0306 INTRODUCTION TO VLSI DESIGN UNIT I INTRODUCTION TO MOS CIRCUITS Why VLSI? Integration improves the design: o lower parasitics = higher speed; o lower power; o physically smaller. Integration reduces

More information

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141

EECS 151/251A Spring 2019 Digital Design and Integrated Circuits. Instructors: Wawrzynek. Lecture 8 EE141 EECS 151/251A Spring 2019 Digital Design and Integrated Circuits Instructors: Wawrzynek Lecture 8 EE141 From the Bottom Up IC processing CMOS Circuits (next lecture) EE141 2 Overview of Physical Implementations

More information

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI

Integrated diodes. The forward voltage drop only slightly depends on the forward current. ELEKTRONIKOS ĮTAISAI 1 Integrated diodes pn junctions of transistor structures can be used as integrated diodes. The choice of the junction is limited by the considerations of switching speed and breakdown voltage. The forward

More information

PAPER SOLUTION_DECEMBER_2014_VLSI_DESIGN_ETRX_SEM_VII Prepared by Girish Gidaye

PAPER SOLUTION_DECEMBER_2014_VLSI_DESIGN_ETRX_SEM_VII Prepared by Girish Gidaye Q1a) The MOS System under External Bias Depending on the polarity and the magnitude of V G, three different operating regions can be observed for the MOS system: 1) Accumulation 2) Depletion 3) Inversion

More information

MOSFETS: Gain & non-linearity

MOSFETS: Gain & non-linearity MOFET: ain & non-linearity source gate Polysilicon wire Heavily doped (n-type or p-type) diffusions W Inter-layer io 2 insulation Very thin (

More information

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 3 Ch.1 The Evolution of The Microprocessor 17-Feb-15 1 Chapter Objectives Introduce the microprocessor evolution from transistors to

More information

Logic Design (Part 1) Transistors & Gates (Chapter 3)

Logic Design (Part 1) Transistors & Gates (Chapter 3) Agenda next 3 weeks: Inside a microprocessor Logic Design (Part 1) Transistors & Gates (Chapter 3) Based on slides McGrawHill Additional material 2004/2005/2006 Lewis/Martin Additional material 2008 Roth

More information

EE 330 Lecture 5. Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic

EE 330 Lecture 5. Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic EE 330 Lecture 5 Other Logic Styles complex logic gates pass transistor logic Improved evice Models Review from Last Time MOS Transistor Qualitative iscussion of n-channel Operation Source Gate rain rain

More information

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad

EE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University

More information

Physical Structure of CMOS Integrated Circuits

Physical Structure of CMOS Integrated Circuits Physical Structure of CMOS Integrated Circuits Dae Hyun Kim EECS Washington State University References John P. Uyemura, Introduction to VLSI Circuits and Systems, 2002. Chapter 3 Neil H. Weste and David

More information

Mathematics and Science in Schools in Sub-Saharan Africa

Mathematics and Science in Schools in Sub-Saharan Africa Mathematics and Science in Schools in Sub-Saharan Africa SEMICONDUCTORS What is a Semiconductor? What is a Semiconductor? Microprocessors LED Transistors Capacitors Range of Conduciveness The semiconductors

More information

Unit-1. MOS Transistor Theory

Unit-1. MOS Transistor Theory VLSI DESIGN -EEE Unit-1 MOS Transistor Theory VLSI DESIGN UNIT I Contents: 1.1 Historical Perspective 1.2 What is VLSI? - Introduction 1.3 VLSI Design Flow 1.4 Design Hierarchy 1.5 Basic MOS Transistor

More information

Chapter # 1: Introduction

Chapter # 1: Introduction Chapter # : Randy H. Katz University of California, erkeley May 993 ฉ R.H. Katz Transparency No. - The Elements of Modern Design Representations, Circuit Technologies, Rapid Prototyping ehaviors locks

More information

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha

ECE520 VLSI Design. Lecture 2: Basic MOS Physics. Payman Zarkesh-Ha ECE520 VLSI Design Lecture 2: Basic MOS Physics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture Semiconductor

More information

Logic Restructuring Revisited. Glitching in an RCA. Glitching in Static CMOS Networks

Logic Restructuring Revisited. Glitching in an RCA. Glitching in Static CMOS Networks Logic Restructuring Revisited Low Power VLSI System Design Lectures 4 & 5: Logic-Level Power Optimization Prof. R. Iris ahar September 8 &, 7 Logic restructuring: hanging the topology of a logic network

More information

UNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts.

UNIT III VLSI CIRCUIT DESIGN PROCESSES. In this chapter we will be studying how to get the schematic into stick diagrams or layouts. UNIT III VLSI CIRCUIT DESIGN PROCESSES In this chapter we will be studying how to get the schematic into stick diagrams or layouts. MOS circuits are formed on four basic layers: N-diffusion P-diffusion

More information

Digital Systems Laboratory

Digital Systems Laboratory 2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD chk034@eng.ucsd.edu Lecture #2 1 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing

More information

VLSI Designed Low Power Based DPDT Switch

VLSI Designed Low Power Based DPDT Switch International Journal of Electronics and Communication Engineering. ISSN 0974-2166 Volume 8, Number 1 (2015), pp. 81-86 International Research Publication House http://www.irphouse.com VLSI Designed Low

More information

Sticks Diagram & Layout. Part II

Sticks Diagram & Layout. Part II Sticks Diagram & Layout Part II Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 11/6/2007 MOSFETs Lecture 6 BJTs- Lecture 1 Reading Assignment: Chapter 10 More Scalable Device Structures Vertical Scaling is important. For example,

More information

Lecture 4 - Digital Representations III + Transistors

Lecture 4 - Digital Representations III + Transistors Lecture 4 - Digital Representations III + Transistors Video: Seems like a natural extension from images no? We just have a new dimension (time) Each frame is just an image made up of pixels Display n frames

More information

Chapter 2 : Semiconductor Materials & Devices (II) Feb

Chapter 2 : Semiconductor Materials & Devices (II) Feb Chapter 2 : Semiconductor Materials & Devices (II) 1 Reference 1. SemiconductorManufacturing Technology: Michael Quirk and Julian Serda (2001) 3. Microelectronic Circuits (5/e): Sedra & Smith (2004) 4.

More information

Intro to Electricity. Introduction to Transistors. Example Circuit Diagrams. Water Analogy

Intro to Electricity. Introduction to Transistors. Example Circuit Diagrams. Water Analogy Introduction to Transistors Transistors form the basic building blocks of all computer hardware. Invented by William Shockley, John Bardeen and Walter Brattain in 1947, replacing previous vaccuumtube technology

More information

Lecture # 23 Diodes and Diode Circuits. A) Basic Semiconductor Materials B) Diode Current and Equation C) Diode Circuits

Lecture # 23 Diodes and Diode Circuits. A) Basic Semiconductor Materials B) Diode Current and Equation C) Diode Circuits EECS 42 ntro. Digital Electronics, Fall 2003 EECS 42 ntroduction to Digital Electronics Lecture # 23 Diodes and Diode Circuits A) Basic Semiconductor Materials B) Diode Current and Equation C) Diode Circuits

More information

EE 330 Lecture 5. Other Logic Styles Improved Device Models Stick Diagrams

EE 330 Lecture 5. Other Logic Styles Improved Device Models Stick Diagrams EE 330 Lecture 5 Other Logic Styles Improved evice Models Stick iagrams Review from Last Time MOS Transistor Qualitative iscussion of n-channel Operation ulk Source Gate rain rain Gate n-channel MOSFET

More information

Digital Design and System Implementation. Overview of Physical Implementations

Digital Design and System Implementation. Overview of Physical Implementations Digital Design and System Implementation Overview of Physical Implementations CMOS devices CMOS transistor circuit functional behavior Basic logic gates Transmission gates Tri-state buffers Flip-flops

More information

APPLICATION TRAINING GUIDE

APPLICATION TRAINING GUIDE APPLICATION TRAINING GUIDE Basic Semiconductor Theory Semiconductor is an appropriate name for the device because it perfectly describes the material from which it's made -- not quite a conductor, and

More information

UNIT-VI FIELD EFFECT TRANSISTOR. 1. Explain about the Field Effect Transistor and also mention types of FET s.

UNIT-VI FIELD EFFECT TRANSISTOR. 1. Explain about the Field Effect Transistor and also mention types of FET s. UNIT-I FIELD EFFECT TRANSISTOR 1. Explain about the Field Effect Transistor and also mention types of FET s. The Field Effect Transistor, or simply FET however, uses the voltage that is applied to their

More information

The Design and Realization of Basic nmos Digital Devices

The Design and Realization of Basic nmos Digital Devices Proceedings of The National Conference On Undergraduate Research (NCUR) 2004 Indiana University Purdue University Indianapolis, Indiana April 15-17, 2004 The Design and Realization of Basic nmos Digital

More information

Power Bipolar Junction Transistors (BJTs)

Power Bipolar Junction Transistors (BJTs) ECE442 Power Semiconductor Devices and Integrated Circuits Power Bipolar Junction Transistors (BJTs) Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Bipolar Junction Transistor (BJT) Background The

More information

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1 Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar

More information

ECE/CoE 0132: FETs and Gates

ECE/CoE 0132: FETs and Gates ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will

More information

SYNTHESIS OF COMBINATIONAL CIRCUITS

SYNTHESIS OF COMBINATIONAL CIRCUITS HPTER 6 SYNTHESIS O OMINTIONL IRUITS 6.1 Introduction oolean functions can be expressed in the forms of sum-of-products and productof-sums. These expressions can also be minimized using algebraic manipulations

More information

Shorthand Notation for NMOS and PMOS Transistors

Shorthand Notation for NMOS and PMOS Transistors Shorthand Notation for NMOS and PMOS Transistors Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V ds = V d V s = V gs - V gd Source and drain are symmetric diffusion

More information

Solid State Devices- Part- II. Module- IV

Solid State Devices- Part- II. Module- IV Solid State Devices- Part- II Module- IV MOS Capacitor Two terminal MOS device MOS = Metal- Oxide- Semiconductor MOS capacitor - the heart of the MOSFET The MOS capacitor is used to induce charge at the

More information

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD?

Improved Inverter: Current-Source Pull-Up. MOS Inverter with Current-Source Pull-Up. What else could be connected between the drain and V DD? Improved Inverter: Current-Source Pull-Up MOS Inverter with Current-Source Pull-Up What else could be connected between the drain and? Replace resistor with current source I SUP roc i D v IN v OUT Find

More information

EECE 481. MOS Basics Lecture 2

EECE 481. MOS Basics Lecture 2 EECE 481 MOS Basics Lecture 2 Reza Molavi Dept. of ECE University of British Columbia reza@ece.ubc.ca Slides Courtesy : Dr. Res Saleh (UBC), Dr. D. Sengupta (AMD), Dr. B. Razavi (UCLA) 1 PN Junction and

More information

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras Lecture - 39 Latch up in CMOS We have been discussing about the problems in CMOS, basic

More information

EE 330 Lecture 5. Basic Logic Circuits Complete Logic Family Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic

EE 330 Lecture 5. Basic Logic Circuits Complete Logic Family Other Logic Styles. Improved Device Models. complex logic gates pass transistor logic EE 330 Lecture 5 asic Logic Circuits Complete Logic Family Other Logic Styles complex logic gates pass transistor logic Improved Device Models Review from Last Time The key patents that revolutionized

More information

Semiconductor Devices

Semiconductor Devices Semiconductor Devices - 2014 Lecture Course Part of SS Module PY4P03 Dr. P. Stamenov School of Physics and CRANN, Trinity College, Dublin 2, Ireland Hilary Term, TCD 3 th of Feb 14 MOSFET Unmodified Channel

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC

More information

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1

EE 330 Lecture 7. Design Rules. IC Fabrication Technology Part 1 EE 330 Lecture 7 Design Rules IC Fabrication Technology Part 1 Review from Last Time Technology Files Provide Information About Process Process Flow (Fabrication Technology) Model Parameters Design Rules

More information

Basic Electronics. Introductory Lecture Course for. Technology and Instrumentation in Particle Physics Chicago, Illinois June 9-14, 2011

Basic Electronics. Introductory Lecture Course for. Technology and Instrumentation in Particle Physics Chicago, Illinois June 9-14, 2011 Basic Electronics Introductory Lecture Course for Technology and Instrumentation in Particle Physics 2011 Chicago, Illinois June 9-14, 2011 Presented By Gary Drake Argonne National Laboratory Session 3

More information

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Jack Keil Wolf Lecture Lec 3: January 24, 2019 MOS Fabrication pt. 2: Design Rules and Layout http://www.ese.upenn.edu/about-ese/events/wolf.php

More information

Layout - Line of Diffusion. Where are we? Line of Diffusion in General. Line of Diffusion in General. Stick Diagrams. Line of Diffusion in General

Layout - Line of Diffusion. Where are we? Line of Diffusion in General. Line of Diffusion in General. Stick Diagrams. Line of Diffusion in General Where are we? Lots of Layout issues Line of diffusion style Power pitch it-slice pitch Routing strategies Transistor sizing Wire sizing Layout - Line of Diffusion Very common layout method Start with a

More information

ECE380 Digital Logic. Logic values as voltage levels

ECE380 Digital Logic. Logic values as voltage levels ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the

More information

CHAPTER FORMULAS & NOTES

CHAPTER FORMULAS & NOTES Formulae For u SEMICONDUCTORS By Mir Mohammed Abbas II PCMB 'A' 1 Important Terms, Definitions & Formulae CHAPTER FORMULAS & NOTES 1 Intrinsic Semiconductor: The pure semiconductors in which the electrical

More information

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness

Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness MIT International Journal of Electronics and Communication Engineering, Vol. 4, No. 2, August 2014, pp. 81 85 81 Design Simulation and Analysis of NMOS Characteristics for Varying Oxide Thickness Alpana

More information