Digital Systems Laboratory

Transcription

1 2012 Fall CSE140L Digital Systems Laboratory Lecture #2 by Dr. Choon Kim CSE Department, UCSD Lecture #2 1

2 Digital Technologies CPU(Central Processing Unit) GPU(Graphics Processing Unit) DSP(Digital gnal Processor) SoC(System on Chip) FPGA (Field Programmable Gate Array) ASIC (Application Specific Integrated Circuit) Custom Designs etc. 2

3 DE1 Board Kit 3

4 FPGAs (Field Programmable Gate Arrays) Programmable Logic Block Switches -SRAM based (Flash memory) -Antifuse Switch Matrix Wiring Channels Disadvantages: Penalty on area, density, speed Advantages: Flexibility, low startup costs, low risk, revisions without changing the hardware 4

5 Periodic table Periodic Table Lecture #2 5

6 Transistors: licon Transistors are built out of silicon, a semiconductor Pure silicon is a poor conductor (no free charges) Doped silicon is a good conductor (free charges) n-type (free negative charges, electrons) p-type (free positive charges, holes) Free electron Free hole As B - licon Lattice n-type 1-<6> p-type 6

7 MOS Transistors Metal oxide silicon (MOS) transistors: Polysilicon (used to be metal) gate Oxide (silicon dioxide) insulator Doped silicon source gate drain Polysilicon O 2 n n p substrate gate source drain nmos 1-<7> 7

8 Transistors: nmos Gate = 0, it is OFF (source and drain are disconnected) source gate GND drain Gate = 1, it is ON (channel between source and drain) Source= 0 => Drain=0 Source=1 => Drain=0.8 (Poor one) source gate V DD drain n p n substrate n channel p n substrate GND GND 1-<8> 8

9 Transistors: pmos pmos transistor is just the opposite ON when Gate = 0 Source =0 => Drain = 0.2 (Poor zero) Source =1 => Drain = 1 OFF when Gate = 1 Polysilicon source gate drain O 2 p p n substrate gate source drain 1-<9>

10 Transistor Function g = 0 g = 1 nmos g d s d s OFF d s ON pmos g s d s d ON s d OFF 1-<10> 10

11 Transistor Function nmos transistors pass good 0 s, so connect source to GND pmos transistors pass good 1 s, so connect source to V DD inputs pmos pull-up network output nmos pull-down network 1-<11> 11

12 CMOS Gate Structure inputs pmos pull-up network output nmos pull-down network 1-<12> 12

13 CMOS Gates: NOT Gate NOT V DD A Y = A A Y Y A P1 Y N1 GND A P1 N1 Y 0??? 1??? 1-<13>

14 CMOS Gates: NOT Gate NOT V DD A Y = A A Y Y A P1 Y N1 GND A P1 N1 Y 0 ON OFF 1 1 OFF ON 0 1-<14>

15 CMOS Gates: NAND Gate A B NAND Y = AB Y A B Y A B P2 P1 Y N1 N2 A B P1 P2 N1 N2 Y <15>

16 CMOS Gates: NAND Gate A B NAND Y = AB Y A B Y A B P2 P1 Y N1 N2 A B P1 P2 N1 N2 Y 0 0 ON ON OFF OFF ON OFF OFF ON OFF ON ON OFF OFF OFF ON ON 0 1-<16>

17 NOR Gate Q: How do you build a three-input NOR gate? 1-<17> 17

18 Homework: Build other gate using CMOS Q: How do you build AND gate? Q: How do you build OR gate? Q: How do you build XOR gate? Q: How do you build XNOR gate? etc. 1-<19> 19

19 Transmission Gates nmos pass 1 s poorly pmos pass 0 s poorly Transmission gate is a better switch passes both 0 and 1 well When EN = 1, the switch is ON: A is connected to B When EN = 0, the switch is OFF: A is not connected to B A EN EN B 1-<20>

20 Noise Anything that degrades the signal E.g., resistance, power supply noise, coupling to neighboring wires, etc. Example: a gate (driver) could output a 5 volt signal but, because of resistance in a long wire, the signal could arrive at the receiver with a degraded value, for example, 4.5 volts Driver Noise Receiver 5 V 4.5 V 1-<21>

21 Logic Levels Driver Receiver Logic High Output Range V O H Output Characteristics V DD NM H Input Characteristics Logic High Input Range Forbidden Zone V IH V IL Logic Low Output Range V O L NM L GND Logic Low Input Range 1-<22>

22 V DD Scaling Chips in the 1970 s and 1980 s were designed using V DD = 5 V As technology improved, V DD dropped Avoid frying tiny transistors Save power 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, Be careful connecting chips with different supply voltages 1-<23>

23 Logic Family Examples Logic Family V DD V IL V IH V OL V OH TTL 5 ( ) CMOS 5 (4.5-6) LVTTL 3.3 (3-3.6) LVCMOS 3.3 (3-3.6) <24>

24 Power Consumption Power = Energy consumed per unit time Two types of power consumption: Dynamic power consumption Static power consumption 1-<25>

25 Dynamic Power Consumption Power to charge transistor gate capacitances The energy required to charge a capacitance, C, to V DD is CV DD 2 If the circuit is running at frequency f, and all transistors switch (from 1 to 0 or vice versa) at that frequency, the capacitor is charged f/2 times per second (discharging from 1 to 0 is free). P dynamic = ½CV DD2 f 1-<26>

26 Static Power Consumption Power consumed when no gates are switching It is caused by the quiescent supply current, I DD, also called the leakage current Thus, the total static power consumption is: P static = I DD V DD 1-<27>

27 Power Consumption Example Estimate the power consumption of a wireless handheld computer V DD = 1.2 V C = 20 nf f = 1 GHz I DD = 20 ma 1-<28>

28 Power Consumption Example Estimate the power consumption of a wireless handheld computer V DD = 1.2 V C = 20 nf f = 1 GHz I DD = 20 ma P = ½CV DD2 f + I DD V DD = ½(20 nf)(1.2 V) 2 (1 GHz) + (20 ma)(1.2 V) = 14.4 W 1-<29>

29 Homework Can you implement a logic with NAND or NOR gate(s) only? Why? Lecture #2 30

30 Multiplexers -If S is 0, then I 0 will pass and I 1 is blocked. Thus, y=i 0. -Likewise, if S is 1, y=i 1. 31

31 More than 2-to-1 Multiplexers -We can also make a 4:1 MUX using three 2:1 MUX A B 0 MUX 1 0 Z S 0 MUX Z C D 0 MUX 1 1 S 1 If S 1 S 0 = 00, then S 1 will select MUX from A and B. nce S 0 =0, Z= A S1 S0 Z 0 0 A 0 1? 1 0? 1 1? 32

32 Multiplexers -We can make 4:1 and above MUXes too. -With 4 inputs, our selector needs to have two bits. 33

33 Question: What is the relation between number of inputs and the min. number of bits of selector? 34

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36 4-bit Ripple Carry Adders -Chain 4 1-bit full adders together. A3A2A1A0 + B3B2B1B0 = C4 S3S2S1S0 -Connect the carry-out of the previous adder and the carry-in of the next adder. -Worst delay path (critical path): from A 0, B 0, or C 0 to S 3, or C 4 37

37 Critical Path for worst delay Propagation from C 0 to C C 0 C 4 38

38 Lecture #2 39

39 Welcome to Verilog Lecture #2 40

40 Introduction to Verilog HDL Home work(reading materials) Warning: Some information contained in the following reading materials(or any material in general) may be incorrect and not working. Only way to verify the correctness of the information is to test it by simulating and synthesizing using our Altera Quartus SW & HW kit. 1. [Quartus II example with Verilog]: Note: You can do this without understanding of Verilog. Follow the instructions described in tut_quartus_intro_verilog_de1 This is the same homework in Lecture#1 except Verilog is used as a design entry instead of Schematic diagram. 2. [Tutorial for beginner]: Follow Verilog short tutorial to make yourself familiar with this new design entry methodology. 3. [Manual]: intro_verilog_manual 4. [Short Reference Card]: Two-page Card Multiple-page Card 5. In addition, there are numerous Verilog information & tutorials available on the web in doc, book, & video format. The Verilog on wiki is an excellent place to learn the background. This Verilog Tutorial is one of tutorial sites. You can use whatever you feel comfortable. 41