Device Technology( Part 2 ): CMOS IC Technologies

Transcription

1 1 Device Technology( Part 2 ): CMOS IC Technologies Chapter 3 : Semiconductor Manufacturing Technology by M. Quirk & J. Serda Saroj Kumar Patra, Department of Electronics and Telecommunication, Norwegian University of Science and Technology ( NTNU )

2 2 Objectives 1. Explain the basic characteristics of CMOS technology, including the field effect transistor, biasing and the CMOS inverter. 2. Explain the difference between enhancement and depletion mode MOSFETs.

3 3 CMOS IC Technology The Field Effect Transistor MOSFETs nmosfet pmosfet Biasing the nmosfet Biasing the pmosfet CMOS Technology BiCMOS Technology Enhancement and Depletion-Mode

4 4 Two Types of MOSFETs pmosfet (p-channel) Source Drain p + p + n-type silicon substrate Drain nmosfet (n-channel) Source Drain n + n + p-type silicon substrate Drain Substrate Substrate Source Figure 3.15 Quirk & Serda Source

5 5 Biasing Circuit for an NMOS Transistor S 1 V GG = V Open gate (no charge) Source Drain n + n + p-type silicon substrate Lamp (no conduction) Figure 3.16 Quirk & Serda V DD = V

6 6 NMOS Transistor in Conduction Mode S 1 V GG = V Positive charge e- Source n + n + Holes p-type silicon substrate Drain I DS Lamp e- e- Figure 3.17 Quirk & Serda V DD = V

7 7 Example of Characteristics Curves of an N-channel MOSFET 600 Linear Region Saturation Region V GS = +5V Drain Current, I DS ( a) V GS = +4V V GS = +3V V GS = +2V V GS = +1V Drain-Source Voltage, V DS (volts) Figure 3.18 Quirk & Serda

8 8 Biasing Circuit for a P-Channel MOSFET S 1 V GG = V Open gate (no charge) Source p + p + Drain n-type silicon substrate Lamp (no conduction) Figure 3.19 Quirk & Serda V DD = -3.0 V

9 9 PMOS Transistor in Conduction Mode S 1 V GG = V Negative charge e- Source Drain I DS p + p + Electrons n-type silicon substrate Lamp e- e- Figure 3.20 Quirk & Serda V DD = V

10 10 Schematic of a CMOS Inverter + V DD G S pmosfet D Input Output D G S nmosfet Figure 3.21 Quirk & Serda -V SS

11 11 Top View of CMOS Inverter n-type silicon substrate Polysilicon n-well p-well +V DD S G D D G S -V SS Metal p + p + n + n + pmosfet nmosfet Figure 3.22 Quirk & Serda

12 12 Cross-section of CMOS Inverter Interlayer Oxide pmosfet Metal nmosfet G G +V DD S D D S -V SS n + p + p + n + n + p + p-well n-type silicon substrate Field oxide Figure 3.23 Quirk & Serda

13 13 BiCMOS Chips used in the Control of a Simple Heating System CPU Setpoint Output Digital side BiCMOS DAC 0-5 V + 48 VDC AMP Analog side Drive signal Heating element Process chamber Temperature sensor Input Feedback BiCMOS ADC 0-5 V AMP mv Measured signal Figure 3.24 Quirk & Serda

14 14 Simple BiCMOS Inverter CMOS section Bipolar section Q1 Q3 INPUT Q2 OUTPUT Q4 Figure 3.25 Quirk & Serda Redrawn from H. Lin, J. Ho, R. Iyer, and K. Kwong, Complementary MOS-Bipolar Transistor Structure, IEEE Transactions Electron Devices, ED-16, 11 Nov. 1969, p

15 15 Comparison of Enhancement and Depletion Mode MOSFETs MOSFET Type Mode Standby Condition V GG Switching Requirements nmos Enhancement Off + nmos Depletion On - pmos Enhancement Off - Physical Structure Source Drain n + n + p-type silicon substrate Source Drain n p-type + silicon substrate n + p-type silicon substrate Source Drain p + p + pmos Depletion On + n-type silicon substrate Source Drain p + p + n-type silicon substrate Figure 3.26 Quirk & Serda

16 16 Latchup in CMOS Devices pmosfet nmosfet V SS S G D D G S V DD n+ p+ p+ n+ n+ p+ RW RS T1 p-well T2 n-type substrate Parasitic Junction Transistors within a CMOS Structure Figure 3.27 Quirk & Serda

17 17 Integrated Circuit Products Linear IC Products Operational Amplifier Voltage Regulator Stepper Motor Driver Digital IC Products Volatile Memory RAM DRAM SRAM MPU or CPU Digital IC Products (continued) Nonvolatile Memory ROM PROM EPROM EEPROM ASIC PLD PAL PLA MPGA FPGA

18 18 g{tç~ léâ