PESIT Bangalore South Campus

Transcription

1 INTERNAL ASSESSMENT TEST 2 Date : 19/09/2016 Max Marks: 40 Subject & Code : Analog and Digital Electronics (15CS32) Section: III A and B Name of faculty: Deepti.C Time : 8:30 am-10:00 am Note: Answer five complete questions each of 8 marks, one from each part PART 1 1. Describe the working principle of 3:8 decoder. Show that using a 3-to--8 decoder and multi input OR gate. the following Boolean Expressions can be realised F1(A,B,C) = Σm (1,2,4,5), F2 (A, B, C) = m (1,5,7) Solution: 3 to 8 decoder Definition -1M, Truth Table-2M, Basic gates circuit -2M, Problem - 3M 3 to 8 decoder takes 3-bit binary data as input, and produces logic 1 on its binary equivalent number line. For example if ABC is 101 then Y5 line is active ( 1 ) and remaining lines are 0 s. (8 Marks)

2 2. a) Realize a logic circuit for Octal to binary encoder. (4 Marks) Solution: Truth Table-1M, Equation-1M,Basic gates circuit -2M An octal to binary encoder has 2 3 = 8 input lines D 0 to D 7 and 3 output lines Y 0 to Y 2. Below is the truth table for an octal to binary encoder. From the truth table, the outputs can be expressed by following Boolean Function. Y 0 = D 1 + D 3 + D 5 + D 7 Y 1 = D 2 + D 3 + D 6 + D 7 Y 2 = D 4 + D 5 + D 6 + D 7

3 b) What is a magnitude comparator? Design one bit comparator using basic gates. Write the truth table and logic expressions. Solution: Definition -1M,Truth Table-1M,Basic gates circuit -1M,Equation -1M (4 Marks) Comparators with three output terminals and checks for three conditions i.e greater than or less than or equal to is magnitude comparator. A comparator used to compare two bits, i.e., two numbers each of single bit is called a single bit comparator. It consists of two inputs for allowing two single bit numbers and three outputs to generate less than, equal and greater than comparison outputs.

4 3. a)give the HDL implementation of 2:1 MUX using dataflow modeling Solution: Module statement and Port declaration 2M,Multiplexer function 2M module mux2x1_df(mout,a,b, S) input A,B,S; output mout; assign mout= S? A : B; endmodule b) Write a 4: 1 MUX Verilog program using conditional 'assign' and 'case' statement. Solution: Module statement and Port declaration 2M,Case statement 2M module mux4x1_bh (i0,i1,i2,i3,select,y) input i0,i1,i2,i3; input [1:0] select; output y; reg y; or i1 or i2 or i3 or select) case (select) 2'b00: y = i0; 2'b01: y = i1; 2'b10: y = i2; 2'b11: y = i3; endcase endmodule (4 Marks) (4 Marks)

5 4. a) Design and implement a Full adder using PAL (5Marks) Solution: Full adder Truth Table or Equations=2M,PAL Circuit -3M The output expressions of a full adder are: S = Σ m(1, 2, 4, 7) Co = Σ m(3, 5, 6, 7) Full adder is realized using PAL as shown below:

6 b) Differentiate between PROM, PAL and PLA. (3 Marks) Solution Each difference 1Mark(1*3=3 Marks)

7 5. What are the differences between BJT and FET? Explain the construction, principle and working of n channel JFET Solution: (Differences -2M,Construction -2M,Diagram and Principle-2M,Working -2M) (8 Marks) i. BJTs are bipolar devices, in which there is a flow of both majority and minority carriers. FETs are unipolar devices, where only the majority carriers flow. ii. BJTs are current-controlled devices; FETs are voltage-controlled devices. iii. Terminals of a BJT are called the emitter, base, and collector. The terminals of an FET are called source, grain, and gate. iv. FETs have higher input impedance compared to BJTs. Therefore, FETs produce larger gains. Figure shows the circuit of n-channel JFET with normal polarities. The two PN junctions at the sides form two depletion layers. The current conduction by charge carriers (i.e. electrons) is through the channel between the two depletion layers and out of the drain. The width and hence resistance of this channel can be controlled by changing the input voltage V GS. The greater the reverse voltage V GS, the wider will be the depletion layer and narrower will be the conducting channel. The narrower channel means greater resistance and hence source to drain current decreases. Thus JFET operates on the principle that width and hence resistance of the conducting channel can be varied by changing the reverse voltage V GS. Case-i: When a voltage V DS is applied between drain and source terminals and voltage on the gate is zero, the two PN junctions at the sides of the bar establish depletion layers. The electrons will flow from source to drain through a channel between the depletion layers. The size of the depletion layers determines the width of the channel and hence current conduction through the bar. Case-ii: When a reverse voltage V GS is applied between gate and source terminals, the width of depletion layer is increased. This reduces the width of conducting channel, thereby increasing the resistance of n-type bar. Consequently, the current from source to drain is decreased. On the other hand, when the reverse bias on the gate is decreased, the width of the depletion layer also decreases. This increases the width of the conducting channel and hence source to drain current.

8 6. Explain the V-I characteristics of an n channel JFET and define its various conditions. (8 Marks) Solution: Drain characteristics Diagram-2M,Transfer Characteristics Diagram -2M,4 Regions Description -2M,Operation-2M The characteristics curve of an N channel JFET transistor shown below is the graph of the drain current, ID versus the gate-source voltage, VGS. This curve represents the transconductance, or simply the gain, of the transistor. The Regions that make up the characterstics are the following: Cutoff Region- This is the region where the JFET transistor is off, meaning no drain current, I D flows from drain to source. Ohmic Region- This is the region where the JFET transistor begins to show some resistance to the drain current, Id that is beginning to flow from drain to source. This is the only region in the curve where the response is linear. Saturation Region- This is the region where the JFET transistor is fully operation and maximum current, for the voltage, VGS, that is supplied is flowing. During this region, the JFET is On and active. Breakdown Region- This is the region where the voltage, VDD that is supplied to the drain of the transistor exceeds the necessary maximum. At this point, the JFET loses its ability to resist current because too much voltage is applied across its drain-source terminals. The transistor breaks down and current flows from drain to source.

9 7. With a neat diagram, explain construction and characteristics of N-channel depletion MOSFET. Solution: Construction Diagram -2M, Drain characteristics Diagram-2M,Transfer Characteristics Diagram -2M,Explanation-2M (8 Marks) In this device a thin layer of N type silicon is deposited just below the gate insulating layer, and forms a conducting channel between source and drain. Therefore when the gate source voltage V GS is zero, current (in the form of free electrons) can flow between source and drain. The gate is totally insulated from the channel by the layer of silicon dioxide. Operation of a Depletion Mode MOSFET In the N channel device, when the gate is made negative with respect to the source, it has the effect of creating a depletion area, free from charge carriers, beneath the gate. This restricts the depth of the conducting channel, so increasing channel resistance and reducing current flow through the device. It is also possible to operate the transistor in enhancement mode. This is done by making the gate positive instead of negative. The positive voltage on the gate attracts more free electrons into the conducing channel, while at the same time repelling holes down into the P type substrate. The more positive the gate potential, lower is the channel resistance. Increasing positive bias therefore increases current flow.

10 8. What are the differences between JFETs and MOSFETs? Briefly describe the operation of CMOS inverter with a neat diagram (8 Marks) Solution: Differences -2M, CMOS Diagram -2M, Circuit-2M, Operation -2M JFET High input impedance It can be operated only in depletion mode High gate current High drain resistance Conductivity is controlled by the reverse biasing of the gate MOSFET Very high input impedance It can be operated in both depletion mode and enhancement mode Low gate current Low drain resistance. Conductivity is controlled by the carriers induced in the channel. A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain terminals. When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic low.

11 PART 5 9. Figure Q9 below shows a biasing configuration using DE-MOSFET. Given that the saturation drain current is 8 ma and pinch off voltage is -5v.Determine the drain source voltage, drain current and gate source voltage (8 Marks) Figure Q9 Solution: ID equation-2m, VGS =2M, ID value-2m,vds-2m The gate source voltage V GS =2V The polarity of the voltage applied between the gate and source terminals is such that the MOSFET operates in the enhancement region of its output characteristics In a DE MOSFET I D =I DSS (1-V GS /Vp) 2 Now IDSS = 8mA, V GS =2V, V P =-5V Substituting in the above equation I D =15.68 ma Applying Kirchhoff s Law to the output side of the circuit, V DD - I D R D - V DS =0 Therefore V DS =11.728V

12 10. Calculate the value of operating point for the circuit shown in Figure Q10 given that threshold voltage for the MOSFET is 2V and ID (ON) = 6 ma for VGS= 5 V. (8 Marks) Figure Q10 Solution: ID equation-2m, VGS equation=2m,id value-2m,vds-2m Drain Current in an E MOSFET is given by I D =K ( V GS - V T ) 2 Hence K= I Don ( V GSon - V T ) 2 =0.66 ma/ V 2 Gate source voltage in the feedback configuration is given by V GS = V DD - I D R D = I D Substituting this value of VGS in the equation for ID we get I D =K ( V GS - V T ) 2 =0.66 *10^-3( I D -2) 2 =9.3 ma VDS = I D =5.7V

13 * * * * * * *