ELEC Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5)
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1 ELE igital Logic ircuits Fall 2015 Logic Synthesis (hapters 2-5) Vishwani. grawal James J. anaher Professor epartment of Electrical and omputer Engineering uburn University, uburn, L vagrawal@eng.auburn.edu Fall 2015, Nov 6... ELE Lecture 6 1
2 Logic Synthesis efinition: To design a logic circuit such that it meets the specifications and can be economically manufactured: Performance meets delay specification, or has minimum delay. ost uses minimum hardware, smallest chip area, smallest number of gates or transistors. Power meets power specification, or consumes minimum power. Testablility has no redundant (untestable) logic and is easily testable. Fall 2015, Nov 6... ELE Lecture 6 2
3 Synthesis Procedure Minimization Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level N-OR or NN-NN or NOR-NOR circuit. Technology mapping onsidering design requirements, transform the minimized form into one of the technologically realizable forms: Programmable logic array (PL) Standard cell library Field programmable gate array (FPG) Others... Fall 2015, Nov 6... ELE Lecture 6 3
4 References on Synthesis G. e Micheli, Synthesis and Optimization of igital ircuits, New York: McGraw-Hill, S. evadas,. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, Fall 2015, Nov 6... ELE Lecture 6 4
5 Programmable Logic rray (PL) direct implementation of multi-output function as a two-level circuit in MOS technology. PL styles: NN-NN NOR-NOR Textbook, hapter 5. Fall 2015, Nov 6... ELE Lecture 6 5
6 Example: Two-Output Function Need four products: P1,, P3, P4 F1 F B B Fall 2015, Nov 6... ELE Lecture 6 6
7 Two-Level N-OR Implementation lso known as technology-independent circuit. INPUTS N OR P1 F1 B P3 P4 F2 Fall 2015, Nov 6... ELE Lecture 6 7
8 NN-NN Implementation INPUTS NN NN P1 F1 B P3 F2 P4 Fall 2015, Nov 6... ELE Lecture 6 8
9 NN Gate in nmos Technology V epletion load V Enhancement load V XY XY XY X X X Y Y Y GN GN GN R.. Jaeger and T, N. Blalock, Microelectronic ircuit esign, Boston: McGraw-Hill, 2008, Section Fall 2015, Nov 6... ELE Lecture 6 9
10 NN-NN PL B F1 F2 V V P1 V V P3 V P4 V GN Fall 2015, Nov 6... ELE Lecture 6 10
11 NN-NN PL SHEMTI B F1 F2 INPUTS Transistors at cross-points OUTPUTS P1 P3 Fall 2015, Nov 6... ELE Lecture 6 11 P4 N-plane OR-plane
12 Standard-ell esign Obtain two-level minimized form. Map the design onto predesigned building blocks called standard cells (technology mapping). Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology: 90 nanometer MOS 65 nanometer MOS 45 nanometer MOS... This is known as application-specific integrated circuit (SI). Fall 2015, Nov 6... ELE Lecture 6 12
13 Technology Mapping Find a common logic element, e.g., two-input NN gate or inverter (one-input NN). MSOP is converted into NN-NN circuit. Split larger input gates into two-input NN gates and inverters. over the circuit with standard cells, also split into two-input NN gates and inverters (graph-matching). Fall 2015, Nov 6... ELE Lecture 6 13
14 Typical ell Library Name rea units (cost) Inputs Output function, Z Inverter 2 NN2 3, B NN3 4, B, NN4 5, B,, OI21 4, B, OI21 4, B, OI22 5, B,, XOR 4, B Z = Z = Z = Fall 2015, Nov 6... ELE Lecture 6 14 B B Z = B Z = B + Z = ( + B) Z = B + Z = B + B S. evadas,. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill 1994, Section 7.7, pp
15 NN3 ell in Transistors V Z B GN Fall 2015, Nov 6... ELE Lecture 6 15
16 NN3 ell Graphs irected cyclic Graph (G) (tree) Root Output One-input node (NOT) Two-input node (NN) Fall 2015, Nov 6... ELE Lecture 6 16
17 NN4 ell Fall 2015, Nov 6... ELE Lecture 6 17
18 OI21 ell Fall 2015, Nov 6... ELE Lecture 6 18
19 OI21 ell Fall 2015, Nov 6... ELE Lecture 6 19
20 OI22 ell in Transistors V Pull-up network B Z Pull-down network Observe that in a MOS circuit, any vector of input variables connects the output Z either to GN or to V, giving it a value 0 or 1, respectively. Examining the pull-down network, we notice that the output is connected to GN if B = 1 or =1. That gives the output function as,. The cell, therefore, is OI22. Z = B+ Fall 2015, Nov 6... ELE Lecture 6 20 GN
21 OI22 ell Fall 2015, Nov 6... ELE Lecture 6 21
22 XOR ell Fall 2015, Nov 6... ELE Lecture 6 22
23 NN Graphs for Library ells Name rea units (cost) Inputs NN graph Inverter 2 NN2 3, B NN3 4, B, NN4 5, B,, OI21 4, B, OI21 4, B, OI22 5, B,, XOR 4, B Fall 2015, Nov 6... ELE Lecture 6 23
24 Technology Mapping Procedure Obtain MSOP. onvert to two-level N-OR circuit. Transform to two-level NN-NN circuit. Transform to two-input NN and inverter tree network. Perform an optimal pattern matching to obtain a minimum cost tree covering. Fall 2015, Nov 6... ELE Lecture 6 24
25 Previous Example: 2-Level NN (Slide 8) INPUTS NN NN P1 F1 B P3 F2 P4 Fall 2015, Nov 6... ELE Lecture 6 25
26 Simple Technology Mapping (2) NN2 (3) NN2 (3) F1 NN3 (4) NN3 (4) B (2) NN2 (3) F2 NN2 (3) ost = 24 Fall 2015, Nov 6... ELE Lecture 6 26
27 Optimum Mapping: onvert NN ircuit to irected cyclic Graph (G) P1 F1 B P3 P4 F2 Each node is a NN gate. (NOT 1-input NN) Fall 2015, Nov 6... ELE Lecture 6 27
28 Split G into Trees (Forest) B F1 B F2 ost = 24 Fall 2015, Nov 6... ELE Lecture 6 28
29 Split Nodes With More Than Two Branches (Use NN3, NN4 Graphs) or F2 or F2 NN4 or Fall 2015, Nov 6... ELE Lecture 6 29
30 Uniform Branching (1 or 2) F1 B B F2 ost = 32 Fall 2015, Nov 6... ELE Lecture 6 30
31 Graph Matching (2) OI21 (4) F1 Nodes inserted For pattern matching B NN3 (4) B (2) NN2 (3) NN3 (4) F2 NN2 (3) ost = 22 Fall 2015, Nov 6... ELE Lecture 6 31
32 Technology Mapping OI21 (4) Inverters inserted For pattern matching (2) B (2) NN3 (4) F1 NN3 (4) B (2) NN2 (3) NN2 (3) Fall 2015, Nov 6... ELE Lecture 6 32 F2 ost = 22
33 Mapped ircuit (2) OI21 (4) F1 NN3 (4) NN3 (4) B (2) NN2 (3) F2 NN2 (3) ost = 22 Fall 2015, Nov 6... ELE Lecture 6 33
34 Original Reference K. Keutzer, GON: Technology Binding and Local Optimization by G matching, Proc. 24th esign utomation onf., 1987, pp Fall 2015, Nov 6... ELE Lecture 6 34
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