Design For Test. VLSI Design I. Design for Test. page 1. What can we do to increase testability?

Transcription

1 VLS esign esign for Test esign For Test What can we do to increase ability? He s dead Jim... Overview design for architectures ad-hoc, scan based, built-in in Goal: You are familiar with ability metrics and you know ad-hoc structures as well as scan- based structures. uilt in structures as LO and boundary scan can be applied. increase observability add more pins (?!) add small probe bus, selectively enable different values onto bus use a hash function to compress a sequence of values (e.g., the values of a bus over many clock cycles) into a small number of bits for later read-out cheap read-out of all state information increase controllability use muxes to isolate sub-modules and select sources of data as inputs provide easy setup of internal state esign strategies for (design for ability): ad ad-hoc ing scan scan-based approaches self self- and built-in in ing MicroLab, VLS-23 (/24) MicroLab, VLS-23 (2/24) JMM v.3 JMM v.3 page

2 d-hoc ing # d-hoc ing #2 vdd d-hoc techniques are a collection of ideas aimed at reducing the time. ommon techniques are: partitioning large sequential circuits adding points adding multiplexers providing for easy state access = = = = co 3 3 co 2 2 co co half-adder adder vdd = = = = co 3 3 co 2 2 co co vdd... MicroLab, VLS-23 (3/24) = = = = co 3 3 co 2 2 co co inp control Module bus oriented technique bus unit unit 2 unit 3 unit 4 multiplexer based ing Module control out 2 inp out Module Module Module : {,2}={,} MicroLab, VLS-23 (4/24) Module Module JMM v.3 JMM v.3 page 2

3 Scan-based techniques # dea: : have a in which all registers are chained into one giant shift register which can be ed/ read-out bit serially. Test remaining (combinational) logic by () in, shift in new values for all register bits thus setting up the inputs to the combinational logic (2) clock the circuit once in normal, latching the outputs of the combinational logic back into the registers (3) in, shift out the values of all register bits and compare against expected results. One can shift in new values at the same time (i.e., combine steps and 3).... scan-out L shift out normal/ shift in normal/ scan-in normal/ Scan-based techniques #2 serial scan scan-out L L2 scan-in serial scan chain Scan registers partial serial scan: sometimes it is not area and speed efficient to implement scan in every location where a register is used (signal processing) R L R4 L L R2 L R5 R6 R3 MicroLab, VLS-23 (5/24) MicroLab, VLS-23 (6/24) JMM v.3 JMM v.3 page 3

4 Level sensitive scan design Scan Elements popular approach is the level sensitive scan design technique from T.W. Williams (LSS) c shift- c2 the circuit is level sensitive (steady state response is independent of circuit and wire delays within a circuit): hazard free each register may be converted to a serial shift register T L L 2 T 2 shift- c serial data in shift data into reg reg c2 omb logic normal operation reg shift reg out serial data out LSS scan FF T TE TE TE L T b a TE a b T L L 2 T a b T 2 a L 2 b T 2 MicroLab, VLS-23 (7/24) MicroLab, VLS-23 (8/24) JMM v.3 JMM v.3 page 4

5 Self-Test Techniques: LO Problem: Scan-based approach is great for ing combinational logic but can be impractical when trying to memory blocks, etc. because b of the number of separate values required to get adequate fault f coverage. Solution: use on-chip circuitry to generate data and check the results. an be used at every power-on on to verify correct operation! Linear Feedback Shift Register (LFSR) f i s are not programmable, can eliminate N gates and some XOR gates... = = = =.... c c 2 c 3 c n- c n normal/ FSM Generate pseudo-random data for most circuits by using, e.g., a linear feedback shift register (LFSR). Memory s use more systematic FSMs to create R and T patterns. circuit under FSM okay For pseudo-random input data simply compute some hash of output values and compare against expected value ( signature ) at end of. Memory data can be checked cycle-by by-cycle. + m 2 3 n c x + c2x + c3x cn x + with a small number of XOR gates the cycle time is very fast. ycle through fixed sequence of states (can be as long as 2 n - for some n s). Handy for large modulo-n n counters. different responses for different initial states different responses for different c i pseudo-random sequence generator (PRSG) c n x n MicroLab, VLS-23 (9/24) MicroLab, VLS-23 (/24) JMM v.3 JMM v.3 page 5

6 serial in = Signature nalysis signature analysis is used to compact a data stream into a so called signature different responses for different c i, many well- known R (cyclic redundancy check) polynomials correspond to a specific choice of c s. i = parallel in = = c c = = c 2 = c 2 = c =.... = = n- c n- = MicroLab, VLS-23 (/24) c n z q z 2 q 2 z n- q n- z n q n LFSR Polynomials polynomials for maximal long sequences for n equal up to 32 n f(x),2,3,4,6,7,5,22 +x+x n 5,,2,29 +x 2 +x n,7,2,25,28,3 +x 3 +x n 9 +x 4 +x n 23 +x 5 +x n 8 +x 7 +x n 8 +x 2 +x 3 +x 4 +x n 2 +x+x 4 +x 6 +x n 3 +x+x 3 +x 4 +x n 4,6 +x 3 +x 4 +x 5 +x n 9,27 +x+x 2 +x 5 +x n 24 +x+x 2 +x 7 +x n 26 +x+x 2 +x 6 +x n 3 +x+x 2 +x +x n 32 +x+x 2 +x +x n examples of R s n R 8 +x+x 4 +x 5 +x 7 +x 8 6 +x 2 +x +x MicroLab, VLS-23 (2/24) JMM v.3 JMM v.3 page 6

7 LO # Very popular built-in in structure is the built-in in logic block observation (LO) from Koenemann LO operate in 4 different s parallel register PRSG or signature analysis scan reset LO LO normal operation register of circuit register LO LO normal operation signature PRSG of circuit analysis LO LO normal operation scan of circuit scan LO LO normal operation reset of circuit reset c c scan in LO #2 example of a LO element with polynomials +x+x = = = = = scan out c c function scan reset PRSG or signature analyzer parallel registers MicroLab, VLS-23 (3/24) MicroLab, VLS-23 (4/24) JMM v.3 JMM v.3 page 7

8 Testing V GN -me meter er (measures ) dea: MOS logic should draw no current when it s not switching. So after initializing circuit to eliminate tri-state fights, disable pseudo-nmos gates, etc., the power-supply current should be zero after all signals have settled. System-Level Test: oundary Scan The EEE 49. boundary scan architecture provides a standardized serial scan path through the /O pins of a chip (also called JTG) at the board level, chips obeying the standard may be connected in a variety of series and parallel combinations for board ing (replacing bead of nails) standardized s: connectivity s between components sampling and setting chip /Os distribution an collection of self- or built-in in- results serial interconnect P interconnect Good for detecting bridging faults (shorts). May want to try several different circuit states to ensure all parts of the chip have been observed. MicroLab, VLS-23 (5/24) O pad and boundary cell serial data in MicroLab, VLS-23 (6/24) serial data out JMM v.3 JMM v.3 page 8

9 oundary Scan: Test ccess Port oundary Scan: TP controller The access port (TP) is a definition of the interface that needs to be included in an TK: clock input TMS: select T: date input TO: data output TRST: optional signal for asynchronous reset the TP the architecture data registers T instruction decode instruction registers clocks/control TK TP TMS controller (TRST) TO State machine for the TP controller. TMS is the control signal. -logic reset run-/idle select-r R-scan select-r R-scan capture-r capture-r shift-r shift-r exit-r exit-r pause-r pause-r exit2-r exit2-r update-r update-r MicroLab, VLS-23 (7/24) MicroLab, VLS-23 (8/24) JMM v.3 JMM v.3 page 9

10 FSM state shiftr clockr updater oundary-scan: R nstruction register (R): minimum 2 bits to next R bit data from last cell shiftr clockr updater capture-r shift-r TRST reset exit-r pause-r R bit exit2-r update-r oundary-scan: R TP data register (R) boundary scan registers T internal data register TO bypass register ( bit) boundary scan register is a special case of a data register. t allows circuit board interconnections to be ed, external components ed, and the state of the chip digital /Os to be sampled. The boundary scan register is mandatory. internal data registers are optional and add additional access to the circuit. the bypass register is a bit register used to bypass a whole chip. MicroLab, VLS-23 (9/24) MicroLab, VLS-23 (2/24) JMM v.3 JMM v.3 page

11 oundary-scan: R boundary scan input and output cells in P from chip last cell boundary scan bi-directional cell enable from chip shiftr clockr last cell shiftr clockr to chip last cell shiftr clockr shiftr clockr next cell shiftr clockr next cell next cell updater updater updater updater updater to chip MicroLab, VLS-23 (2/24) out P bidir P oundary scan: instructions Minimum 3 instructions ypass (all ): it is used to bypass any serial data registers in a chip with a bit register. This allows specific chips to be ed in a serial-scan scan chain without having to shift through the accumulated SR stages in all the chips Ex (all ): ing of off chip circuitry sample/pre: places the boundary scan registers (at the chips /O pins) in the R chain, and samples or pres the chips /Os optional recommended instructions: n: : single-step step ing of internal circuitry via the boundary scan registers Runbist: : run internal self-ing procedures within a chip MicroLab, VLS-23 (22/24) JMM v.3 JMM v.3 page

12 oming Up... Next time: Top down design. Hardware description languages, logic synthesis. Readings Weste: 7.3 through (ad-hoc scan-based ing) through (LO) (ddq ( ing) 7.5 (boundary scan) Exercises: VLS-22 Ex vlsi22. (difficulty: easy): calculate the pseudo- random sequence of an LFSR with the implemented polynomial +x+x 3 use the start value x= Result:,3,7,6,5,2,4,,... MicroLab, VLS-23 (23/24) MicroLab, VLS-23 (24/24) JMM v.3 JMM v.3 page 2